Wideband communication using delay line clock multiplier

Abstract

A delay line clock multiplier is disclosed for use in a communication system, in which a delay line is used as a clock multiplier for generating a higher speed clock that may be used, for example, for data sampling. The speed and timing characteristics of the clock delay line are adjusted by controlling the supply voltage to the delay line. because proper synchronization may be achieved at the higher frequencies using an oversampling synchronization approach which in turn is made possible by the delay line clock multiplier which allows for the oversampling of a signal at sub-interval increments.

Description

FIELD OF THE INVENTION

[0002] The present invention relates generally to the field of data communications. Specifically, the present invention relates to a data sampling system which may be used in for example synchronization procedures such as those used in wideband spread spectrum communication.

BACKGROUND OF THE INVENTION

[0003] Spread spectrum communication is a type of signal modulation in which a signal to be transmitted is spread over a bandwidth that substantially exceeds the data transfer rate or the minimum bandwidth required to transmit the signal. Fundamentally, in channels with narrowband noise, increasing the transmitted signal bandwidth decreases the interference effect of such noise since the signal instead of being concentrated in a particular band is now spread out over a much wider band.

[0004] Signal spreading may be achieved using any of a number of different techniques, including direct sequence, frequency hopping or a hybrid combination.

[0005] In direct sequence spread spectrum, a periodic, relatively high frequency, repetitive pseudo-noise code (PN) is mixed with the data signal using XOR gates or a mixer, and the resulting signal is then modulated using, e.g., binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK). This process causes the transmitted signal to be replaced by a very wide bandwidth signal with the spectral equivalent of a noise signal. At the receiver, the demodulation process involves the mixing and multiplying of the same PN code with the received signal. This produces a correlated signal which is maximum when the PN code matches the received signal. The correlated signal is then filtered and demodulated.

[0006] In frequency hopping spread spectrum, the signal stream to be transmitted is shifted in frequency by an amount determined by a code that spreads the signal power over a wide bandwidth. This is accomplished using a PN code controlled frequency synthesizer. In this way, the instantaneous frequency output of the transmitter jumps from one value to another based on the PN code. By changing the instantaneous frequency of the output signal, the output frequency spectrum is effectively spread over the range of the wider bandwidth.

[0007] The PN codes used in direct sequence spread spectrum systems consist of individual units called “chips” which can have two values, either −1/1 in a polar system or 0/1 in a binary system. In general, these PN codes must have a sharp (e.g., one chip wide) autocorrelation peak to allow for proper code synchronization, as well as a low cross-correlation value to allow for more users in the system. Additionally, the codes should be balanced, i.e., the number of ones and zeros may only differ by a maximum of one. This latter requirement allows for good spectral density such that the signal energy may be uniformly spread over the entire frequency band. Codes which may be used in direct sequence spread spectrum systems include Walsh-Hadamard codes, M-sequences, Gold codes and Kasami codes. These codes may be either orthogonal or non-orthogonal.

[0008] One difficulty encountered in spread spectrum systems is achieving proper synchronization, i.e., having the receiver lock onto and synchronize with the bit timing of the transmitter so that the receiver is sampling and segmenting the received signal at the proper bit boundaries intended by the transmitter. One approach to achieving synchronization is disclosed in U.S. Pat. No. 5,727,004 entitled METHOD AND APPARATUS FOR DATA ENCODING AND COMMUNICATION OVER NOISY MEDIA, and assigned to the assignee of the present application, the contents of which are incorporated herein by reference. The synchronization procedure disclosed in U.S. Pat. No. 5,727,004 oversamples the received signal at a number of points which are offset in time by a fraction of the bit interval (i.e., sub-interval). Each of the sampled signals is analyzed to determine which of the bit intervals results in good correlation and therefore represents the proper bit boundaries. The oversampling of the incoming signal at a number of sub-intervals generally requires either a clock or some other timing source running at a multiple of the bit clock in order to sample the signal at subinterval increments.

[0009] The FCC regulations governing electromagnetic radiation limits, 47 CFR § 15.107, 109, 209, . . . place limits on radiated and conducted emissions for both intended and unintended emissions. The term “intended” refers to the intended mode of transmission. For example, in the case of wireless communication, the “intended” mode of transmission is radiated, while the unintended mode of transmission is conducted. Similarly, in the case of wired communication, the “intended” mode of transmission is conducted, while the unintended mode of transmission is radiated.

SUMMARY OF THE INVENTION

[0010] The present invention is directed to a delay line clock multiplier for use in a communication system, such as a spread spectrum system, in which a delay line is used as a clock multiplier for generating a higher speed clock that may be used, for example, for data sampling. The speed and timing characteristics of the clock delay line are adjusted by controlling the supply voltage to the delay line. Additionally, by utilizing the spread spectrum approach, the electromagnetic emissions can be kept below the FCC imposed limits. Generally, as a signal is spread over a wider spectrum utilizing higher frequencies there results a problem in achieving proper synchronization at those higher frequencies. However, utilizing the present invention, a signal may be spread over a wide frequency band because proper synchronization may be achieved at the higher frequencies using an oversampling synchronization approach which in turn is made possible by the delay line clock multiplier which allows for the oversampling of a signal at sub-interval increments.

[0011] According to the present invention, a multiple stage delay line is used as a clock multiplier for generating a high speed clock signal from a relatively low speed clock source. The delay line includes an odd number of delay stages and the output of the last delay stage is connected to the input of the first delay stage in essentially an oscillator or inverter ring configuration. Normally, an inverter ring contains alternating 1s and 0s in the successive stages of the ring. However, the inverter ring of the present invention is perturbed or initialized to contain the same value in two successive stages (e.g. two 1s or two 0s in a row) in order to create a distinctive transition or edge pattern which cycles through the ring.

[0012] The contents of the delay line, i.e., the state of the delay line at a particular stage, which is essentially a square wave with alternating 1s and 0s is input to a phase comparator. The other input to the phase comparator is connected to the slow speed clock signal. The output of the phase comparator is an indication of the relative speeds of the two input signals, viz., the slow speed clock and the delay line contents, and is used to control a voltage adjustment circuit which in turn adjusts one or both of the supply voltages to the delay line to thereby adjust the switching speed of the individual gates or stages that make up the delay line.

[0013] Essentially, the phase comparator and voltage adjustment circuit act to speed up or slow down the delay line to match the slow speed clock signal. If the delay line is running too slow, the supply voltages are adjusted to decrease the voltage difference between them. As a result, the individual gates of the delay line switch a smaller voltage difference in going from high to low (or low to high) and are thus able to switch faster. Conversely, if the delay line is running too fast, the supply voltages are increased so as to increase the voltage difference between them. This slows down the individual gate elements which must now switch a larger voltage difference for each high to low (or low to high) transition. It should be noted that when the delay line and the slow speed clock are properly matched, the speed of the delay line (i.e., the delay through all the stages of the delay line) is actually twice that of the slow speed clock, since each stage in the delay line must include two periods (high and low) to match the square wave slow speed clock signal. The delay through all the stages of the delay line corresponds to one phase of the slow speed clock signal so the delay through the delay line is less than the period of the slow speed clock signal.

[0014] Once the clock delay line is running at the appropriate speed, this in turn establishes the corresponding control voltages which result in that speed. The control voltages are also applied to another delay line (series connected inverters) which is essentially used as a serial shift register causing it in turn to run at the same speed as the first delay line. The input to the second delay line is the serial stream of incoming data, and the individual stages of the second delay line act to oversample the incoming data at a number of successive subintervals. Each of the subinterval samples is latched for subsequent processing and compensated for the inversion of the individual stages introduced by the inverter. In this way, adjusting the control voltage acts to adjust the timing of the delay lines in order to oversample the incoming data signal in order to achieve proper synchronization.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other objects, features and advantages of the invention discussed in the above brief explanation will be more clearly understood when taken together with the following detailed description of an embodiment which will be understood as being illustrative only, and the accompanying drawings reflecting aspects of that embodiment, in which:

[0016] FIG. 1 is a block diagram of a delay line clock multiplier oversampling circuit according to the present invention;

[0017] FIG. 2 is a schematic diagram of a delay line configured as a sampling shift register;

[0018] FIG. 3 is a schematic diagram of a delay line configured as an oscillator;

[0019] FIG. 4 is a schematic diagram of an inverter stage; and

[0020] FIG. 5 is an illustration of the voltage transfer characteristics of an inverter stage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Referring now to FIG. 1, therein is shown a block diagram of a delay line clock multiplier oversampling circuit 10 according to the present invention. The clock multiplier circuit 10 includes a clock source 100 which is also referred to herein as a slow speed clock source since the clock and timing signals generated by the clock multiplier circuit 10 result in a faster speed clock signal than that of clock source 100. In the specific example illustrated in FIG. 1 and described herein, clock source 100 is a 14 MHZ clock; however, it should be understood that the speed of clock source may of course be varied to other frequencies depending on the particular application.

[0022] The output of clock source 100 is applied as an input to phase comparator 102. The other input to phase comparator 102 is connected to the output stage 104 of a delay line 106. The operation of delay line 106 will be described in greater detail below. The function of phase comparator 102 is to produce an output signal on line 108 which is an indication of the relative speeds or phases of the two input signals to the phase comparator 102. The phase comparator output signal is provided to a control voltage adjustment circuit 110 that, depending on the output signal from the phase comparator 102, adjusts the power supply or reference voltages applied to delay line 106.

[0023] Essentially, control voltage adjustment circuit 110 is responsive to the output signal from the phase comparator 102 to either increase or decrease one or more of the power supply voltages supplied to the delay line 106 in order to slow down or speed up the switching operation of delay line 106. As shown in FIG. 3, in one illustrative embodiment the delay line 106 consists of a number of series connected inverters I′1, I′2, . . . followed by a buffer B. Thus, the delay line functions as an oscillator. In the specific embodiment illustrated in FIG. 3, delay line 106 includes 31 inverter stages followed by the buffer B. Further, the output of the buffer B is connected to the input of the first inverter I′1 in order to provide an inverter ring or oscillator. Each of the inverters in delay line 106 is constructed generally according to the circuit diagram of FIG. 4. As shown in FIG. 4, each inverter stage includes a P-channel transistor 402 connected to an N-channel transistor 404. The gate inputs to the transistors 402 and 404 are connected together and act as the input node VIN, while the drains of the two transistors are likewise connected together and act as the output node VOUT.

[0024] The circuit configuration of FIG. 4 acts as an inverter, i.e., a logic high input (1) results in a logic low output (0) and vice versa. The voltage transfer characteristics of the circuit of FIG. 4 are illustrated in FIG. 5 as a function of supply voltage VCC. As shown in FIG. 5, as the supply voltage VCC decreases, the switching speed of the inverter increases since the voltage swing between the logic levels decreases. The control voltage adjustment circuit 110 acts to adjust the supply voltage VCC in order to adjust the switching speed of the individual inverter stages of delay line 106. The circuits such as are shown in FIG. 4 have two supply voltages VCC and GND, with the effective voltage supplied to the circuit being the differential voltage between the two supplies, i.e., VCC−GND. The object of control voltage adjustment circuit 110 is to adjust this differential voltage, which of course may be achieved by modifying one or both of VCC and GND.

[0025] Phase comparator 102 and control voltage adjustment circuit 110 operate to adjust the supply voltage VCC and, thus, the speed of delay line 106 so that the delay time through the 32 stages (31 inverters I′N and buffer B) of delay line 106 is the same as the slow speed clock signal generated by the clock 100.

[0026] The adjusted supply voltage VCC from the control voltage adjustment circuit 110 is also applied to a second delay line 112 (FIGS. 1 and 2). In the illustrative embodiment of FIGS. 1 and 2, the second delay line 112 includes thirty one (31) series-connected inverters I1 through I31. The input of the first inverter I1 is connected to the incoming signal line 114 that transmits the serial data being received. A plurality of output lines D0 through D31 are connected to the second delay line 112 and to a latch 116. The line D0 is connected to the input of inverter I1, while the lines D1 through D31 are connected to the outputs of the respective inverters I1 through I31.

[0027] The latch 116 is triggered by the output from the delay line 106. In the illustrative embodiment, because the clock source 100 operates at 14 MHZ, the output from the delay line serves as a 28 MHZ clock. Thus, the latch operates at the increased frequency, such that the serial data is oversampled. Each bit is sampled 32 times.

[0028] Thus, by adjusting the phase of the delay line 106 through the control voltage adjustment circuit 110, the circuit 10 of the present invention is controlled to oversample the serial data signal in order to achieve proper synchronization.

[0029] From the foregoing, it will be apparent that the system 10 of the present invention serves to oversample an incoming serial data stream in order to achieve proper synchronization between the receiver and transmitter.

[0030] While a form of the invention has been illustrated and described, it will be apparent to those skilled in the art that various modifications and improvements may be made without departing from the spirit and scope of the invention.

Claims

1. A solid-state oscillator comprising an odd number of solid-state inverter devices cascaded in series, each inverter having an input and an output, the output of the last inverter being fed back to the input of the first inverter.

2. In combination with the oscillator of claim, a source of a clock signal; a phase comparator receiving the clock signal as a first input and the input of the first inverter as a second input; the phase comparator producing a difference signal related to the phase difference between its inputs; a voltage generator producing an output voltage and having a control input, the amplitude of the output voltage signal being controlled by a signal applied to the control input, the difference signal being applied to the control input; the inverters having a reference voltage connection, the delay of an inverter being controlled by the value of the voltage applied to the reference voltage connection, the output voltage being applied to reference voltage connection; and a combining circuit combining the outputs of N inverters; the output of the combining circuit being at a frequency which is N times the clock frequency.

3. In combination with the combination of claim 2: M solid state inverter devices cascaded in series to define a delay line, each inverter of the delay line having an input and an output, each inverter having a reference voltage connection, the delay of an inverter being controlled by the value of the voltage applied to the reference voltage connection, the output voltage being applied to reference voltage connections of the inverters; a data signal being applied to the input of the first inventor of the delay line; an M position latch receiving the outputs of the inverters of the delay line, the latch being clocked with the output of the combining circuit; whereby M samples of the data signal are produced at a frequency which is N times the clock frequency.