Wideband Doherty power amplifier

Abstract

The present invention provides a wideband Doherty power amplifier comprising: a main power amplification device; an auxiliary power amplification device arranged in parallel with the main power amplification device; and a coupled phase compensation network configured for compensating a phase shift between the main power amplification device and the auxiliary power amplification device. The phase compensation network comprising a first transmission line section; a second transmission line section extending substantially collinearly with the first transmission line section; and two pairs of end-connected coupled transmission lines connected in parallel between the first transmission line section and the second transmission line section. The provided Doherty power amplifier demonstrated operation at 6 dB back-off between 1.3-2.3 GHz with efficiency in excess of 41%, which can be used in modern and future wireless communication systems which require power amplifiers operating over a wide frequency range.

Description

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

FIELD OF THE INVENTION

The present invention relates to a Doherty power amplifier, and particularly, although not exclusively, to a Doherty power amplifier based on a coupled phase compensation network.

BACKGROUND OF THE INVENTION

Doherty power amplifier (DPA) is widely adopted in modern wireless communication systems as it typically provides high efficiency from 6-dB output power back-off to saturation. Due to the output current generated by the peaking device at the back-off point, the carrier device load impedance can be modulated, thereby achieving an additional efficiency peak. This unique characteristic of the DPA is particularly suitable for modern and emerging communication standards that typically uses modulated signal with high peak to average power ratios (PAPRs). However, the biggest problem with conventional DPA topologies is the narrow bandwidth, which limits its usage. In recent years, bandwidth extension of DPAs have therefore attracted a lot of interest in both academia and industry. The post-matching Doherty power amplifier (PM-DPA), as a solution to broad bandwidth, in general have 40% bandwidth. However, further improvement has been difficult, due mainly to two reasons. Firstly, the peaking branch (peaking fundamental impedance inverter (FII) plus phase compensation network (PCN)) suffers from a large impedance transformation ratio at saturation. This restricts the peaking amplifier bandwidth, thus limiting the load modulation bandwidth. Secondly, conventional FIIs used in DPAs, often have complicated topologies that can introduce large phase delays. Together with phase delay variations over a wide frequency range that limits performance for wideband operation.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a wideband Doherty power amplifier (DPA) is provided. The wideband DPA comprises: a main power amplification device; an auxiliary power amplification device arranged in parallel with the main power amplification device; a first fundamental impedance inverter having an input connected to an output of the main power amplification device through a first DC block; a second fundamental impedance inverter having an input connected to an output of the auxiliary power amplification device through a second DC block; a coupled phase compensation network connected across respective outputs of the first and second fundamental impedance inverters and configured for compensating a phase shift between the main power amplification device and the auxiliary power amplification device. The coupled phase compensation network comprises: a first transmission line section connected with the first fundamental impedance inverter; a second transmission line section connected with the second fundamental impedance inverter; and two pairs of end-connected coupled transmission lines connected in parallel between the first transmission line section and the second transmission line section.

By using the coupled phase compensation network instead of the conventional quarter-wavelength transmission line, the external Q-factor (QE) of the entire peaking branch is reduced. Consequently, the drain termination impedance trajectory of the peaking device is distributed around its optimal value. Hence, a good efficiency/output power performance of the peaking amplifier can be obtained over a significantly wider frequency range and the bandwidth of the DPA can be extended. Measured results of the provided Doherty power amplifier demonstrated operation at 6 dB back-off between 1.3-2.3 GHz (55% fractional bandwidth) with efficiency in excess of 41%. The bandwidth-extended DPA provided by the invention can be used in modern and future wireless communication systems which require power amplifiers operating over a wide frequency range, such as 4G and 5G mobile radio communication systems. The electrical power cost to operate base station power amplifiers will also be reduced significantly for future wireless communication systems.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

Embodiments of the invention are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 shows a high-level circuit diagram of a Doherty power amplifier (DPA) according to one embodiment of the invention;

FIG. 2 shows operation of an asymmetrical drain biased DPA below/at back-off point;

FIG. 3 shows operation of an asymmetrical drain biased DPA at saturation;

FIGS. 4A and 4B show detailed physical design and circuit geometry respectively of a coupled phase compensation network according to one embodiment of the invention;

FIG. 5A shows circuit geometry of an entire peaking branch including a L-type FII coupling with a phase compensation network (PCN) according to an embodiment of the invention;

FIG. 5B shows geometry of an entire peaking branch including a L-type FII coupling with a conventional PCN which is formed with a microstrip line;

FIG. 6 shows an input impedance (Z_{IN_A}) trajectory of the peaking branch of FIG. 5A and an input impedance (Z_{IN_B}) trajectory of the peaking branch of FIG. 5B, respectively;

FIG. 7 shows the electrical length (θ_A) of the peaking branch of FIG. 5A and the electrical length (θ_B) of the peaking branch of FIG. 5B, respectively;

FIGS. 8A and 8B show the optimal impedance of Z_carrier (denoted as Z_opt,c), and Z_peaking (denoted as Z_opt,p) at saturation over the entire operating frequency respectively;

FIGS. 9A-9C show time-domain voltage and current waveforms of the DPA at operating frequencies f_low (1.3 GHz), f₀ (1.8 GHz) and f_high (2.3 GHz) respectively;

FIG. 10 shows the simulated and measured small signal performance of a fabricated DPA at various operating frequencies from 1.3 GHz to 2.3 GHz;

FIG. 11A shows the simulated drain efficiency of the fabricated DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz;

FIG. 11B shows the measured drain efficiencies of the fabricated DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz;

FIG. 12 shows measured gain of the fabricated DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz;

FIG. 13 shows measured adjacent channel power ratios (ACPRs) of the fabricated DPA under modulated signal excitation at various operating frequencies from 1.3 GHz to 2.3 GHz; and

FIGS. 14A-14C shows the normalized power spectral density of the fabricated DPA at operating frequencies f_low (1.3 GHz), f₀ (1.8 GHz) and f_high (2.3 GHz) respectively.

DETAILED DESCRIPTION

In the following description, exemplary embodiments of the present invention are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 shows a high-level circuit diagram of a Doherty power amplifier (DPA) 100 according to one embodiment of the invention. Referring to FIG. 1, the DPA 100 includes an input port (In), an output port (Out), a main power amplification device (“carrier device”) 105C; and an auxiliary power amplification device (“peaking device”) 105P arranged in parallel with the main power amplification device/

The DPA 100 further includes an input power splitter (IPS) 122 having an input connected with the input port, a first (upper) branching network connected between a first output of the IPS 122 and the carrier device 105C and a second (lower) branching network connected between a second output of the IPS 122 and the peaking device 105P.

The first (upper) branching network includes an offset line (OL) 102 having a first end connected to the first output of the IPS 122, an input matching network (IMN) 124a having an input connected to an output of the OL 102, a stabilized network (SN) 128a having an input connected to an output of the IMN 124a through a DC block 126a and an output connected to an input of the carrier device 105C.

The second (lower) branching network includes an IMN 124b having an input connected to a second output of the IPS 122, a SN 128b having an input connected to an output of the IMN 124b through a DC block 126b and an output connected to an input of the pealing device 105P.

The carrier device 105C may be biased by a biasing network. The carrier device 105C may include a power transistor which can be of any suitable types for different power applications. The power transistor of the carrier device 105C may have a drain terminal and a gate terminal being with a drain bias 131d and a gate bias 131g respectively. Preferably, the drain bias is 20V such that the carrier device 105C is biased to operate as a Class AB amplifier (in particular a deep Class AB amplifier).

The peaking device 105P may be biased by a biasing network. The peaking device 105P may include a power transistor which can be of any suitable types for different power applications. The power transistor of the peaking device 105P may have a drain terminal and a gate terminal with a drain bias 132d and a gate bias 132g respectively. Preferably, the drain bias is 28V and the peaking device 105C is biased to operate as a Class C amplifier (in particular a deep Class C amplifier).

It should be understood that the power transistors used for forming the carrier and peaking devices can be of any types.

The asymmetrical drain biased carrier device 105C (at 20 V) and peaking device 105P (at 28 V) can be considered as two current sources in phase quadrature. Hence, the peaking device 105P behaves as a voltage controlled current source providing the current to modulate the load impedance of the carrier device 105C for Doherty behavior.

The DPA 100 further includes a fundamental impedance inverter (FII) 182a having an input connected to an output of the carrier device 105C though a DC block 186a, a FII 182b having an input connected to an output of the peaking device 105P though a DC block 186b, a coupled phase compensation network (PCN) 184 connected across respective outputs of the two FII 182a, 182b; and a post matching network (PMN) 188 having an input connected to a combining node (C.N.) combining signals from the carrier device and the peaking device, and an output connected to the output port, to which a load may be connected.

FIG. 2 shows operation of the asymmetrical drain biased DPA 100 below/at back-off point. As shown in FIG. 2, at the back-off point, only the carrier device is conducting, the output impedance of the carrier branch is equal to the impedance at the combing node, which in turn equal to the load impedance. Below the back-off point, the output impedance toward the peaking branch should be infinite to prevent power leakage from the carrier branch. Therefore, the fundamental load impedances at the back-off point should satisfy the following conditions:

$\begin{array}{cc}{R}_{\mathrm{carrier},\mathrm{back}-\mathrm{off}}\mathrm{at}{f}_0=R_{C.N.}=R_L,R_{\mathrm{peaking},\mathrm{back}-\mathrm{off}}\mathrm{at}{f}_0=\infty & \left(1\right)\end{array}$

where R_{carrier,back-off} refers to the output impedance of carrier branch at back-off point, R_C,N refers to impedance at the combing node, R_{peaking,back-off} refers to the output impedance of the peaking branch at back-off point, R_L is the load impedance and f₀ is the fundamental operation frequency.

FIG. 3 shows operation of the asymmetrical drain biased DPA 100 at saturation. As shown in FIG. 3, at saturation, both the carrier and peaking devices are conducting, the output impedances of carrier branch and peaking branch are both 2R_L in order to maintain an R_C.N. impedance. Therefore, the fundamental load impedances at saturation should satisfy the following conditions

$\begin{array}{cc}{R}_{\mathrm{carrier},sat}\mathrm{at}{f}_0=2R_L,R_{peaking,sat}\mathrm{at}{f}_0=2R_L& \left(2\right)\end{array}$

where R_carrier,sat refers to the output impedance of carrier branch at saturation, R_{peaking,back-off} refers to the output impedance of the peaking branch at saturation.

The function of the PCN is to compensate for the 90° phase shift between the carrier and peaking devices which may cause mismatch at the fundamental frequency, so as to increase the operating bandwidth. The impedance looking into the PCN should be set to 2R_L in order to prevent power loss in the peaking branch. After that, the PMN transforms the “real-to-real” impedance from system load (R₀) to combining node (R_C.N.).

Design of the carrier FII needs to satisfy the load conditions at back-off and at saturation simultaneously. Since the carrier FII adopts a L-type configuration, which can be readily modelled as an LC tank-equivalent circuit, the drain impedance seen by the carrier device, Z_carrier, can be expressed as

$\begin{array}{cc}{Z}_{carrier}=j\omega L+\frac{1}{j\omega C+\frac{1}{R}}& \left(3\right)\end{array}$

This expression can be expanded into its real and imaginary parts as

$\begin{array}{cc}{Z}_{carrier}=\frac{R}{1+R^2{\omega }^2{C}^2}+j\left(\mathrm{\omega L}-\frac{\omega C}{{\omega }^2{C}^2+\frac{1}{R^2}}\right)& \left(4\right)\end{array}$

The load modulation result at back-off point is R═R_L. The load modulation result at saturation is R=(1+α)R_L, where α=P_sat,p/P_sat,c, with P_sat,c and P_sat,p referring to the saturated carrier and peaking fundamental power. It is required that the real part of Z_carrier does not change at ω=ω₀=2πf₀, that is:

$\begin{array}{cc}\frac{R_L}{1+R_L^2{\omega }_0^2{C}^2}=\frac{\left(1+\alpha \right)R_L}{1+{\left(\left(1+\alpha \right)R_L\right)}^2{\omega }_0^2{C}^2}& \left(5\right)\end{array}$

Eq. (5) can be rearranged in terms of coo which is given by

$\begin{array}{cc}{\omega }_0=\sqrt{\frac{1}{\left(1+\alpha \right)C^2{R}_L^2}}& \left(6\right)\end{array}$

Therefore, the real part of Z_carrier, at ω₀, has a relationship with R_L and α, given by

$\begin{array}{cc}\mathrm{Re}\left\{Z_{carr\mathrm{ier},\mathrm{sat}}\right\}=\frac{R_L\left(1+\alpha \right)}{2+\alpha }& \left(7\right)\end{array}$

Based on the above, the value of C can be determined by Eq. (6) and L should be tuned to an appropriate value based on load-pull data.

FIGS. 4A and 4B show detailed physical design and circuit geometry of the coupled PCN 184 of FIG. 1 respectively. As shown in FIGS. 4A and 4B, the PCN 184 includes a transmission line section 184A, a transmission line section 184B extending generally collinearly with the transmission line section 184A, two pairs of end-connected coupled transmission lines 185, 186 connected in parallel between the transmission line section 184A and the transmission line section 184B. Each of the end-connected coupled lines 185, 186 is substantially symmetrical.

The pair of end-connected coupled transmission lines 185 includes a transmission line section 185A with a first end and a second end; and a transmission line section 185B with a first end and a second end, arranged adjacent and in parallel with the transmission line section 185A. The transmission line section 185A generally extends substantially perpendicularly from the transmission line section 184A. The transmission line section 185B generally extends substantially perpendicularly from the transmission line section 184B.

The pair of end-connected coupled transmission lines 186 includes a transmission line section 186A with a first end and a second end; and a transmission line section 186B with a first end and a second end, arranged adjacent and in parallel with the transmission line section 186A. The transmission line section 186A generally extends perpendicularly from the transmission line section 184A. The transmission line section 186B generally extends perpendicularly from the transmission line section 184B.

The first end of the transmission line section 185A is directly connected with the first transmission line section 184A. The first end of the transmission line section 185B is directly connected with the transmission line section 184B. The second end of the transmission line section 185A and the second end of the transmission line section 185B are directly connected with each other to provide the end-connected coupling. In other words, the transmission line sections 184A, 184B, 185A, 185B form a continuous transmission line.

The first end of the transmission line section 186A is directly connected with the first transmission line section 184A. The first end of the transmission line section 186B is directly connected with the transmission line section 184B. The second end of the transmission line section 186A and the second end of the transmission line section 186B are directly connected with each other to provide the end-connected coupling. In other words, the transmission line sections 184A, 184B, 186A, 186B form a continuous transmission line.

Each pair of the end-connected coupled lines 185, 186 has even and odd mode impedances Z_ei, Z_oi respectively, and an electrical length of θ_i, where i=1, 2. The ABCD matrix parameters for each pair of the end-connected coupled lines 185, 186 in series are:

$\begin{array}{cc}\left[\begin{array}{cc}{A}_i& B_i\\ C_i& D_i\end{array}\right]=\left[\begin{array}{cc}\frac{Z_{\mathrm{ei}}\cot {\theta }_i-Z_{\mathrm{oi}}\tan {\theta }_i}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}& \frac{2{\mathrm{jZ}}_{\mathrm{ei}}{Z}_{\mathrm{oi}}}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}\\ \frac{2j}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}& \frac{Z_{\mathrm{ei}}\cot {\theta }_i-Z_{\mathrm{oi}}\tan {\theta }_i}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}\end{array}\right]\left(i=1,2\right)& \left(8\right)\end{array}$

The ABCD matrix of its parallel equivalence can then be found by:

$\begin{array}{cc}\left[\begin{array}{cc}{A}_{\mathrm{ip}}& B_{\mathrm{ip}}\\ C_{\mathrm{ip}}& D_{\mathrm{ip}}\end{array}\right]=\left[\begin{array}{cc}{A}_i& C_i\\ \frac{1}{B_i}& D_i\end{array}\right]\left[\text{⁠}\begin{array}{cc}\frac{Z_{\mathrm{ei}}\cot {\theta }_i-Z_{\mathrm{oi}}\tan {\theta }_i}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}& \frac{2j}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}\\ -\frac{j\left(Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i\right)}{2Z_{\mathrm{ei}}{Z}_{\mathrm{oi}}}& \frac{Z_{\mathrm{ei}}\cot {\theta }_i-Z_{\mathrm{oi}}\tan {\theta }_i}{Z_{\mathrm{ei}}\cot {\theta }_i+Z_{\mathrm{oi}}\tan {\theta }_i}\end{array}\right]\left(i=1,2\right)& \left(9\right)\end{array}$

With the parallel equivalent ABCD matrices, the two end-connected coupled lines 185, 186 can then be analyzed by cascading the ABCD matrices. The parallel equivalent ABCD matrix of the two end-connected coupled lines 185, 186 can then be expressed as:

$\begin{array}{cc}\left[\begin{array}{cc}{A}_{ParaPCN}& B_{ParaPCN}\\ C_{ParaPCN}& D_{ParaPCN}\end{array}\right]=\left[\text{⁠}\begin{array}{cc}\frac{Z_{e1}\cot {\theta }_1-Z_{o1}\tan {\theta }_1}{Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1}& \frac{2j}{Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1}\\ -\frac{j\left(Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1\right)}{2Z_{e1}{Z}_{o1}}& \frac{Z_{e1}\cot {\theta }_1-Z_{o1}\tan {\theta }_1}{Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1}\end{array}\right]\left[\text{⁠}\begin{array}{cc}\frac{Z_{e2}\cot {\theta }_2-Z_{o2}\tan {\theta }_2}{Z_{e2}\cot {\theta }_2+Z_{o2}\tan {\theta }_2}& \frac{2j}{Z_{e2}\cot {\theta }_2+Z_{o2}\tan {\theta }_2}\\ -\frac{j\left(Z_{e2}\cot {\theta }_2+Z_{o2}\tan {\theta }_2\right)}{2Z_{e2}{Z}_{o2}}& \frac{Z_{e2}\cot {\theta }_2-Z_{o2}\tan {\theta }_2}{Z_{e2}\cot {\theta }_2+Z_{o2}\tan {\theta }_2}\end{array}\right]& \left(10\right)\end{array}$

Afterwards, the ABCD matrix parameters of the cascaded PCN 184 can be obtained by performing the following transformation:

$\begin{array}{cc}\left[\begin{array}{cc}{A}_{\mathrm{PCN}}& B_{\mathrm{PCN}}\\ C_{\mathrm{PCN}}& D_{\mathrm{PCN}}\end{array}\right]=\left[\begin{array}{cc}{A}_{P\mathrm{araPCN}}& \frac{1}{C_{ParaPCN}}\\ B_{\mathrm{ParaPCN}}& \frac{1}{D_{ParaPCN}}\end{array}\right]& \left(11\right)\end{array}$

Assuming that the networks are lossless, reciprocal and symmetrical, to achieve the ideal conditions of A_PCND_PCN−B_PCNC_PCN=1, A_PCN=D_PCN=1, the value of C_PCN must equal to 0, that is:

$\begin{array}{cc}\frac{Z_{e1}\cot {\theta }_1-Z_{o1}\tan {\theta }_1}{Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1}\frac{2j}{Z_{e2}\cot {\theta }_1+Z_{o2}\tan {\theta }_1}+\frac{Z_{e2}\cot {\theta }_2-Z_{o2}\tan {\theta }_2}{Z_{e2}\cot {\theta }_2+Z_{o2}\tan {\theta }_2}\frac{2j}{Z_{e1}\cot {\theta }_1+Z_{o1}\tan {\theta }_1}=0& \left(12\right)\end{array}$

In this embodiment, the end-connected coupled lines 185, 186 may be selected to have identical geometry and same characteristics such as even and odd mode impedances and electrical length. By letting Z_e1=Z_e2=Z_e, Z_o1=Z_o2=Z_o, and θ₁=θ₂=θ, it can then be found that the following relationship between Z_e, Z_o and θ should be satisfied.

$\begin{array}{cc}\cot \theta =\sqrt{Z_e{Z}_o}& \left(13\right)\end{array}$

The PCN 184 can also be considered to be two micro-strip lines in parallel with the addition of electrical coupling. This additional coupling leads to a smaller external quality factor (Q_E). When viewed on the Smith chart, the trajectory can be seen to follow a “circular path”. This path can be seen as the peaking device being able to operate over a wider frequency range. It should be noted that the characteristics (Z_e, Z_o and θ) of the selected coupled lines should satisfy the condition in Eq. (13).

Furthermore, the electrical length of the PCN 184 should be equal to the phase difference between the carrier and peaking devices 150C, 150P. This is calculated using the ratio of drain currents, which is given, in polar coordinates, by:

$\begin{array}{cc}\frac{I_c}{I_p}=\alpha e^{j{\theta }_p}& \left(14\right)\end{array}$

where I_c is the drain current of the carrier device, I_p is the drain current of the peaking device, and Θ_p is the phase difference between the carrier and peaking devices.

Therefore, the two transmission lines 184A, 184B should be added to satisfy the phase requirement of the entire PCN.

FIG. 5A shows circuit geometry of an entire peaking branch including a L-type FII coupling with a PCN according to an embodiment of the invention, in which the odd/even mode impedance and electrical length of the two end-connected coupled lines are set equal, namely, Z_e1=Z_e2=124Ω, Z_o1=Z_o2=65.4Ω, and θ₁=θ₂=20°. FIG. 5B shows geometry of an entire peaking branch including a L-type FII coupling with a conventional PCN which is formed with a microstrip line.

It should be note that although in this embodiment, the odd/even mode impedance and electrical length of the two end-connected coupled lines are set equal, in other embodiments, the values of the odd/even mode impedance of the two end-connected coupled lines can be different, that is Z_e1≠Z_e2, Z_o1≠Z_o2.

FIG. 6 shows an input impedance (Z_{IN_A}) trajectory of the peaking branch of FIG. 5A and an input impedance (Z_{IN_B}) trajectory of the peaking branch of FIG. 5B. As shown in FIG. 6, an additional circle within the Smith chart for the Z_{IN_A} trajectory can be seen. This proves that Q_E of the entire peaking branch for the provided PCN is reduced compared with the conventional PCN. Thus, this smaller variation verifies that the coupled PCN can provide a wider bandwidth.

FIG. 7 shows the electrical length (θ_A) of the peaking branch of FIG. 5A and the electrical length (θ_B) of the peaking branch of FIG. 5B, respectively. Both can be seen to have similar electrical lengths. It should be noted that due to parasitic effects of the active device, the entire peaking branch electrical length at center frequency is not necessarily designed to be the ideal 180°.

FIGS. 8A and 8B show the optimal impedance of Z_carrier (denoted as Z_opt,c), and Z_peaking (denoted as Z_opt,p) at saturation over the entire operating frequency respectively, which can be obtained using the load pull simulator in Keysight ADS software. Referring to FIG. 8A, for the carrier device, the selection strategy for Z_opt,c is to find an impedance to achieve the best trade-off performance over the entire operating frequency range. Meanwhile, the imaginary part should be as small as possible. That is because the effect of the L-type FII is movement of the imaginary part of Z_carrier towards the real axis when going from back-off to saturation. Hence, Z_opt,c at saturation is then required to have a small imaginary part. Finally, Z_opt,c is chosen to be 23+j17.5Ω. Referring to FIG. 8B, for the peaking device, it is not wise to select Z_opt,p in conjunction with a large imaginary part because the transistor at 1.3 GHz still exhibits high efficiency even with Z_opt,p being far away from its highest efficiency point. Eventually, Z_opt,p is selected to be 30+j10Ω. With the help of this optimal impedance selection strategy, the DPA can achieve an excellent trade-off in performance between back-off efficiency, saturated efficiency and saturated output power.

FIGS. 9A-9C show time-domain voltage and current waveforms of the DPA at operating frequencies f_low, (1.3 GHz), f₀ (1.8 GHz) and f_high (2.3 GHz) respectively, which are over the entire operating frequency range. It can be seen that at back-off point, the voltage swing reached its maximum amplitude while the current swing reached half its maximum swing. At saturation, both voltage and current reach their maximum swing.

A Doherty power amplifier (DPA) is designed and fabricated based on the circuit diagram of FIG. 1 using Rogers substrates. Experiments and test were performed on the fabricated Doherty power amplifier, results of which are shown in the graphs of FIGS. 10 to 13.

FIG. 10 shows the simulated and measured small signal performance of the fabricated DPA at various operating frequencies from 1.3 GHz to 2.3 GHz. There is good agreement between simulation and measurements. The gain was higher than 10 dB from 1.3 GHz to 2.3 GHz.

FIG. 11A shows the simulated drain efficiency of the fabricated DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz. It can be observed that Doherty behavior was successfully realized over the entire band, and exhibited higher than 44.5% drain efficiency (η) at 6 dB OBO (37 dBm) covering a bandwidth of 1 GHz (1.3 GHz to 2.3 GHz).

FIG. 11B shows the measured drain efficiencies of the DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz. It can be observed that Doherty behavior was successfully realized over the entire band, and exhibited higher than 41% drain efficiency (η) at 6 dB OBO (37 dBm) covering a bandwidth of 1 GHz (1.3 GHz to 2.3 GHz).

FIG. 12 shows measured gain of the fabricated DPA with respect to the output power at various operating frequencies from 1.3 GHz to 2.3 GHz. It can be observed that the gain decreases from 12.1 dB to 9.7 dB with varying output power. The compression point at saturation is less than 3.2 dB over the entire frequency range.

FIG. 13 shows measured adjacent channel power ratios (ACPRs) of the fabricated DPA under modulated signal excitation at various operating frequencies from 1.3 GHz to 2.3 GHz. It can be observed that the lower ACPR performance of the DPA was better than −25.9 dBc at saturation and −22.7 dBc at back-off from 1.3 to 2.3 GHz.

FIGS. 14A-14C shows the normalized power spectral density of the fabricated DPA at operating frequencies f_low (1.3 GHz), f₀ (1.8 GHz) and f_high (2.3 GHz) respectively. The designed DPA was linearized by using digital pre-distortion (DPD) based on the dynamic deviation reduction Volterra series. For the measurement, the linearization was performed at the back-off output power of 37.5 dBm. After linearization, the DPA achieved better than −44.1 dBc (1.3 GHz), −53.3 dBc (1.8 GHz) and −41.6 dBc (2.3 GHz) at back-off, respectively.

The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

The apparatuses and the methods in accordance to embodiments disclosed herein may be implemented using computing devices, computer processors, or electronic circuitries and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software codes running in the computing devices, computer processors, or programmable logic devices can readily be prepared by practitioners skilled in the software or electronic art based on the teachings of the present disclosure.

All or portions of the methods in accordance to the embodiments may be executed in one or more computing devices including server computers, personal computers, laptop computers, mobile computing devices such as smartphones and tablet computers.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

Claims

1. A wideband Doherty power amplifier comprising: a main power amplification device;an auxiliary power amplification device arranged in parallel with the main power amplification device;a first fundamental impedance inverter having an input connected to an output of the main power amplification device through a first DC block;a second fundamental impedance inverter having an input connected to an output of the auxiliary power amplification device through a second DC block;a coupled phase compensation network connected across respective outputs of the first and second fundamental impedance inverters and configured for compensating a phase shift between the main power amplification device and the auxiliary power amplification device;wherein the coupled phase compensation network comprises: a first transmission line section connected with the first fundamental impedance inverter;a second transmission line section connected with the second fundamental impedance inverter; anda first and a second pairs of end-connected coupled transmission lines, both connected in parallel between the first transmission line section and the second transmission line section.

2. The wideband Doherty power amplifier according to claim 1, wherein the compensated phase shift is substantially equal to 90°.

3. The wideband Doherty power amplifier according to claim 1, wherein the first and second pairs of end-connected coupled transmission lines are configured to fulfill a phase requirement given by:

4. The wideband Doherty power amplifier according to claim 1, wherein each of the first and second fundamental impedance inverters has an L-type circuit topology.

5. The wideband Doherty power amplifier according to claim 1, wherein: the first pair of end-connected coupled transmission lines comprises: a third transmission line section extending substantially perpendicularly from the first transmission line section; anda fourth transmission line section extending substantially perpendicularly from the second transmission line section; andthe second pair of end-connected coupled transmission lines comprises: a fifth transmission line section extending substantially perpendicularly from the first transmission line section; anda sixth transmission line section extending substantially perpendicularly from the second transmission line section.

6. The wideband Doherty power amplifier according to claim 5, wherein: the third transmission line section has a first end and a second end;the fourth transmission line section has a first end and second end;the first end of the third transmission line section is directly connected with the first transmission line section;the first end of the fourth transmission line section is directly connected with the second transmission line section; andthe second end of the third transmission line section and the second end of the fourth transmission line section are directly connected with each other.

7. The wideband Doherty power amplifier according to claim 5, wherein: the fifth transmission line section has a first end and a second end;the sixth transmission line section has a first end and second end;the first end of the fifth transmission line section is directly connected with the first transmission line section;the first end of the sixth transmission line section is directly connected with the second transmission line section; andthe second end of the fifth transmission line section and the second end of the sixth transmission line section are directly connected with each other.

8. The wideband Doherty power amplifier according to claim 1, further comprising: an input power splitter having an input connected with an input port of the Doherty power amplifier;a first branching network connected between a first output of the input power slitter and the main power amplification device; anda second branching network connected between a second output of the input power slitter and the auxiliary power amplification device.

9. The wideband Doherty power amplifier according to claim 8, wherein the first branching network includes: an offset line having a first end connected to the first output of the input power splitter;a first input matching network having an input connected to a second end of the offset line;a first stabilized network having an input connected to an output of the first input matching network through a third DC block, and an output connected to the input of the main power amplification device.

10. The wideband Doherty power amplifier according to claim 8, wherein the second branching network includes: a second input matching network having an input connected to the second output of the input power splitter;a second stabilized network having an input connected to an output of the second input matching network through a fourth DC block, and an output connected to the input of the auxiliary power amplification device.

11. The wideband Doherty power amplifier according to claim 1, further comprising a post matching network having: an input connected to a combining node combining a main current signal from the main power amplification device and an auxiliary signal from the auxiliary power amplification device; andan output connected to the output port.

12. The wideband Doherty power amplifier according to claim 1, wherein the main power amplification device is biased to operate as a Class AB amplifier.

13. The wideband Doherty power amplifier according to claim 1, the main power amplification device comprises a transistor.

14. The wideband Doherty power amplifier according to claim 1, wherein the auxiliary power amplification device is biased to operate as a Class C amplifier.

15. The wideband Doherty power amplifier according to claim 1, the auxiliary power amplification device comprises a transistor.

16. The wideband Doherty power amplifier according to claim 1, wherein: the main power amplification device has a main output impedance at saturation; and the auxiliary power amplification device has an auxiliary output impedance at saturation;the main output impedance at saturation and the auxiliary output impedance at saturation are substantially identical and equal to 2RL, where RL is a load impedance at the output port.

17. The wideband Doherty power amplifier according to claim 1, wherein: the main power amplification device has a main output impedance at back-off point; and the auxiliary power amplification device has an auxiliary output impedance at back-off point;the main output impedance at back-off point is substantially equal to RL, where RL is a load impedance at the output port; andthe auxiliary output impedance at back-off point is substantially infinite.

18. An electronic device comprising the wideband Doherty power amplifier according to claim 1.