Patent Grant
7233612
1. Field of the Invention
The present invention relates to a deinterleaver module of a wireless receiver, for example a IEEE 802.11a based Orthogonal Frequency Division Multiplexing (OFDM) receiver.
2. Background Art
Local area networks historically have used a network cable or other media to link stations on a network. Newer wireless technologies are being developed to utilize OFDM modulation techniques for wireless local area networking applications, including wireless LANs (i.e., wireless infrastructures having fixed access points), mobile ad hoc networks, etc. In particular, the IEEE Standard 802.11a, entitled “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHz Band”, specifies an OFDM PHY for a wireless LAN with data payload communication capabilities of up to 54 Mbps. The IEEE 802.11a Standard specifies a PHY system that uses fifty-two (52) subcarrier frequencies that are modulated using binary or quadrature phase shift keying (BPSK/QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM.
Hence, the IEEE Standard 802.11a specifies an OFDM PHY that provides high speed wireless data transmission with multiple techniques for minimizing data errors.
A particular concern in implementing an IEEE 802.11 based OFDM PHY in hardware involves providing a cost-effective, compact device the can be implemented in smaller wireless devices. Hence, implementation concerns typically involve cost, device size, and device complexity.
For example, the IEEE Standard 802.11a specifies that interleaving is performed on the transmit data stream using a two-step permutation to improve bit error rate performance in the presence of frequency-selective channel fading. In particular, adjacent coded bits are mapped in the first permutation onto non-adjacent subcarrier frequencies (i.e., “tones”) to prevent frequency-selective fading; depending on the modulation scheme used by the transmitter (e.g., BPSQ, QPSK, 16-QAM, or 64-QAM), adjacent coded bits also may be mapped in the second permutation onto alternately less and more significant bits in the constellation map (I+jQ) to reduce long runs of low reliability (i.e., least significant bit) values.
Hence, an OFDM PHY receiver configured for receiving IEEE 802.11a based wireless signals requires a deinterleaver to perform the two inverse permutations applied to the code words prior to transmission. However, the block size for each interleaving permutation is variable, based on the modulation scheme utilized by the transmitter (e.g., BPSK, QPSK, 16-QAM, or 64-QAM). Moreover, the mere storage of the serial data stream into successive memory locations of a random memory, followed by two-stage manipulation of the serial data stream following storage thereof to recover the deinterleaved data, may create substantial latency delays within the deinterleaver due to the processing overhead and the substantial memory read/write access operations necessary to deinterleave the received serial stream.
In addition, inefficient implementation of the OFDM PHY receiver may result in increased cost. For example, an inefficient implementation of the OFDM PHY may rely on a large read only memory (ROM) or inefficient state machines for deinterleaving operations such as memory addressing or deinterleaving sequence generation, increasing the size and cost of the device.
There is a need for an arrangement that enables a wireless transceiver host to perform deinterleaving of a received serial stream in an efficient and economical manner.
There also is a need for an arrangement that enables a wireless transceiver host to perform deinterleaving of a received serial stream with minimal latency.
These and other needs are attained by the present invention, where a deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. Write enable signals, bit selection signals, and address signals for each of the code word bits are generated based on applying logical operands to a cascaded sequence of successively delayed signals synchronous with a local clock signal. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.
Hence, deinterleaving operations can be efficiently implemented based on implementing serial-input/parallel output write/read operations within partitioned memory banks.
One aspect of the present invention provides a method in a deinterleaver module for deinterleaving interleaved data into deinterleaved data. The method includes generating a write enable signal for writing a code word fragment into one of a group of partitioned memory banks. The write enable signal has a period based on a prescribed maximum number of code word bits for the code word fragment relative to a prescribed clock, and an enable duration having a number of clock cycles corresponding to a prescribed number of the code word bits in the code word fragment based on a prescribed modulation of the interleaved data. The method also includes generating an address signal based on the prescribed modulation and a selected offset, including selectively incrementing, based on the prescribed modulation, the address signal by the selected offset each clock signal concurrent with the enable duration. The method also includes generating successively delayed copies of the write enable signal and the address signal for others of the group of partitioned memory banks, and storing a first group of the code word fragments into the respective group of partitioned memory banks, by supplying to the respective partitioned memory banks the address and write enable signals and the successively delayed copies thereof. Each code word fragment is associated with a corresponding prescribed subcarrier frequency and has the number of code word bits, and the storing includes writing the code word bits for each code word fragment into respective selected locations of the corresponding memory bank based on the corresponding address signal and the corresponding write enable signal.
Another aspect of the present invention provides a deinterleaver module including a group of partitioned memory banks, a write logic module, and an output module. The group of partitioned memory banks is configured for storing interleaved data as a respective group of successive code word fragments, each code word fragment associated with a prescribed subcarrier frequency and having a prescribed number of code word bits based on a prescribed modulation of the interleaved data, each memory bank configured for storing a selected bit of a corresponding received code word fragment at a corresponding selected location. The write logic module is configured for storing, for each memory bank, the code word bits for each corresponding code word fragment into the respective selected locations based on the prescribed modulation and the corresponding prescribed subcarrier frequency. The write logic module includes a data selection logic module configured for generating bit selection signals for storage of the code word bits according to selected bit deinterleaving sequences, based on at least selected ones of a plurality of successively delayed copies of a write enable signal component. The write logic module also includes a multi-phase write enable logic generator configured for generating the successively delayed copies of the write enable signal, the write enable signal having a period based on a prescribed maximum number of code word bits for the code word fragment relative to a prescribed clock and an enable duration having a number of clock cycles corresponding to a prescribed number of the code word bits in the code word fragment based on a prescribed modulation of the interleaved data. The output module is configured for outputting deinterleaved data from the partitioned memory banks by retrieving, in parallel, code word bits stored at a corresponding selected address for the memory banks.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout and wherein:
The disclosed embodiment will be described with reference to an overview of an IEEE 802.11 OFDM transceiver, followed by a detailed description of the deinterleaver implemented according to an embodiment of the present invention.
The receiver module 50 also includes a dynamic range adjustment module 54. The dynamic range adjustment module 54 is configured for adjusting the gain of the compensated signal samples to a prescribed dynamic range for optimized signal processing, thereby outputting adjusted signal samples according to the prescribed dynamic range.
The rotor circuit 56 is configured for compensating between a local receiver carrier frequency (i.e., local oscillator) and the remote transmitter carrier frequency (i.e., remote oscillator) used to transmit the wireless signal. In particular, the course/fine frequency offset estimator 58 is configured for estimating the difference in the frequency between the local receiver carrier frequency and the remote receiver carrier frequency, and supplying this difference to a phasor circuit 60; the phasor circuit 60 converts the difference value to a complex phasor value (including angle information) which is supplied to the rotor circuit 56. Hence, the rotor circuit 56 rotates the adjusted signal samples based on the complex phasor value, and outputs rotated signal samples.
The circular buffer 62 is configured for buffering the rotated signal samples. In particular, the beginning of a data packet is not guaranteed to be located at the same position within the sequence of rotated signal samples. Hence, the rotated signal samples are stored in the circular buffer 62 in a manner such that any data sample within a prescribed duration (e.g., one maximum-length data packet) can be located and retrieved from the circular buffer 62. Once the circular buffer 62 reaches capacity, any new signal sample to be stored in the circular buffer 62 is overwritten over the oldest stored signal sample. Hence, the circular buffer 62 enables the receiver 50 to adjust the “starting point” of the data packet within the sequence of rotated signal samples.
The Fast Fourier Transform (FFT) circuit 64 is configured for converting the time-based sequence of rotated signal samples into a frequency domain-based series of prescribed frequency points (i.e., “tones”); according to the disclosed embodiment, the FFT circuit 64 maps the rotated signal samples to a frequency domain of fifty-two (52) available tones.
In particular, the available fifty-two (52) tones are used to transport information: four (4) tones are used as pilot tones, and the remaining forty-eight (48) tones are data tones, where each tone may carry from one to six (1-6) bits of information. According to the IEEE 802.11a/g specification, the physical layer data packet should include a short training sequence, a long training sequence, a signal field (indicating the data rate and length of the payload, and coded at the lowest data rate of 6 Mbps), and the payload data symbols encoded in one of eight data rates from 6 Mbps to 54 Mbps. The FFT circuit 64 determines the data rate from the signal field, and recovers the data tones.
The FFT circuit 64 outputs a group of tone data to a buffer 66, illustrated as a first buffer portion 66a, a second buffer portion 66b, and a switch 66c: the FFT circuit 64 alternately outputs the groups of tone data between the buffer portions 66a and 66b, enabling the switch 66 to output one group of tone data from one buffer portion (e.g., 66a) while the FFT circuit 64 is outputting the next group of tone data into the other buffer portion (e.g., 66b). Note actual implementation may utilize addressing logic to execute the functions of the switch 66c.
Since certain tones output by the FFT 64 may have encountered fading due to signal attenuation and distortion on the wireless channel, equalization is necessary to correct the fading. The frequency domain equalizer 68 is configured for reversing the fading encountered by the tones in order to provide equalized tones. Channel information is obtained by the channel estimator 70 from the long training sequence in the IEEE 802.11 preamble; the channel information is used by the channel estimator 70 to estimate the channel characteristics; the estimated channel characteristics are supplied to the frequency equalizer 68 to enable equalization of each tone.
In addition to the coarse and fine frequency offset estimator 58, the phasor circuit 60 and the channel estimator 70, the receiver module 50 also includes a timing synchronization module 72, a frequency tracking block 74, a channel tracking block 76, and a timing correction block 78 for controlling signal conditioning to ensure the received signal samples are decoded properly to accurately recover the data symbols.
The decoding portion 80 includes a digital slicer module 82, a deinterleaver 84, and a Viterbi decoder 86. The digital slicer module recovers up to 6 bits of symbol data from each tone, based on the data rate specified in the signal field in the preamble. The deinterleaver 84 performs the converse operation of the transmitter interleaver circuit, and rearranges the data back into the proper sequence of deinterleaved data. The Viterbi decoder 86 is configured for decoding the deinterleaved data into decoded data, in accordance with the IEEE 802.11 specification.
The descrambler circuit 90 is configured for recovering the original serial bit stream from the decoded data, by descrambling a 127-bit sequence generated by the scrambler of the transmitter, according to the IEEE 802.11 specification. The descrambler circuit 90 utilizes a scrambling seed, recovered from the service field of the data packet by the seed estimation circuit 92, for the descrambling operation. The signal field information from the preamble also is stored in a signal field buffer 94, configured for storing the length and data rate of the payload in the data packet. Overall control of the components of the receiver 50 is maintained by the state machine 96.
Hence, the serial bit stream recovered by the descrambler circuit 90 is output to an IEEE 802.11 compliant Media Access Controller (MAC).
The deinterleaver module 84 receives an input data stream 108 of interleaved data for a code word. In particular, packet data, in the form of bits, is interleaved prior to transmission for two reasons: map adjacent coded bits onto non-adjacent subcarrier frequencies (i.e., tones) to combat frequency-selective fading; and map adjacent coded bits onto alternately less and more significant bits in the constellation to combat white noise. Hence, the input data stream to the deinterleaver module 84 is composed of fragments 110 of a code word (e.g., 48-bit code word, 96-bit code word, 192-bit code word, or 288-bit code word), where each fragment is transmitted on a particular tone. Hence, collection of the fragments over the forty-eight (48) data tones enables recovery of the original code word.
The disclosed deinterleaver 84 is configured for storing the code word fragments from the interleaved data stream 108 into the partitioned memory banks 100 in a serial sequence, described below, where a group of successive code word fragments 110 are stored into the respective group of partitioned memory banks. Hence, the first group of the first, second, third, and fourth code word fragments 110 are stored in the memory banks 100a, 100b, 100c, and 100d, respectively, and the next group of the fifth, sixth, seventh, and eighth code word fragments 110 are stored in the memory banks 100a, 100b, 100c, and 100d, respectively.
The write logic module 102 includes a latch circuit module section 112, a data select logic module 114, a write enable logic module 116, and a write address logic module 118. As described below, these modules enable the code word bits for a given code word fragment 110 to be stored into the corresponding memory bank (e.g., 100a) based on the prescribed modulation and the corresponding prescribed subcarrier frequency, enabling deinterleaving operations to be performed based on writing the code word bits into the partitioned memory banks 100. Hence, the output module 104 outputs deinterleaved data 120 by retrieving, in parallel, code word bits from a given address (rd_addr) of the memory banks 100.
As described in detail below, the write logic module 102 is configured for storing, for each memory bank (e.g., 100a), code word bits for a corresponding code word fragment into respective selected locations based on the modulation in use (e.g., BPSK, QPSK, 16-QAM, or 64-QAM), and the subcarrier frequency (i.e., tone number) used for modulating the corresponding code word fragment. Bit selection is performed by the data selection logic module 114 outputting bit selection signals 106 (m_seli), write enable for storage of data into the memory banks 100 is performed by the write enable logic module 116 outputting write enable signals 107 (wr_eni), and address selection is performed by the write address logic module 118 outputting write address signals 109 (w_addri).
The bit selection signals (e.g., msel_0) supplied to the multiplexers 126 are generated by the data selection logic module 114. As described below with respect to
The multiplexer 140 is configured for outputting the deinterleaving sequence for the appropriate modulation (e.g., no sequence for BPSK, 0-1 sequence for QPSK, 0-1-2-3 or 1-0-3-2 for 16-QAM, and 0-1-2-3-4-5, 2-0-1-5-3-4, or 1-2-0-4-5-3 for 64-QAM). Other sequences also may be used. Although not illustrated in
The successively delayed pulsed signals 111 (e0-e6) are used as inputs to logic circuits within the modules 114, 116, and 118, to generate the bit selection signals 106, the write enable signals 107, and the write address signals 109, respectively. As illustrated in
As illustrated in
Hence, the write enable signals 107 are generated based on applying logic operations to the pulsed signals 111, which serve as components of the write enable signals. As such, the pulsed signals are also referred to as write enable signal components.
As illustrated in
The write address logic module 118 also includes multiplexer based logic 144, and an adder 146. The adder 146 is used to add a prescribed offset to each code word bit that needs to be stored in the memory bank; as illustrated in
Once the first group of code word fragments has been stored, the multiplexer logic 144 selects the next group of available addresses (e.g., “1”) for storage of the next group of code word fragments.
Referring to
In the case of QPSK, illustrated in
At event 176 the code word fragment 108 for the next subcarrier frequency “41” would be latched into the latch circuit module 122b, and the code word bit 190e (41.0) would be written into the memory bank 100b at address “0”, followed by the storage at event 178 of the next code word bit 190f into the memory bank 100b at address “4”.
After the first group of code word fragments for tones 38, 41, 45, and 48 have been stored, the write address logic module 118 increments the address pointer for storage of the code word bits (e.g., 190c and 190d) for the next code word fragment at addresses “1” and “5”, respectively. The storage sequence continues until the last code word fragment is stored corresponding to tone 26.
Note that the code word bits 190g, 190h, 190i, and 190j for the code word fragment 110 corresponding to tone 38 are written according to the bit deinterleaving sequence 132e (“0-1-2-3”), whereas the code word bits 190k, 1901, 190m, and 190n for the code word fragment 110 corresponding to tone 41 are written according to the bit deinterleaving sequence 132e (“1-0-3-2”). As described above, the bit deinterleaving sequence may be selected for the corresponding modulation rate based on the tone number, where each tone number maps to one of a prescribed group of deinterleaving sequences 132 via the deinterleaving sequence logic 130. Hence, the first four-bit output value 120 at event 184 would include the bits “38.0, 41.1, 45.0, and 48.1”, followed by the next four-bit output value at event 186 including the bits “51.0, 54.1, 58.0, 61.1”.
Note, however, that whereas the code word bits for the code word fragments 110 corresponding to tones 38 and 48 are stored according to the sequence 132a (“0-1-2-3-4-5”), the code word bits for the code word fragments 110 corresponding to tones 41 and 45 are stored according to the sequence 132b (“2-0-1-5-34”) and 132c (“1-2-0-4-5-3”), respectively. Hence, while the same addressing scheme is used for the group of code word fragments for the first four tones 38, 41, 45, and 48, different deinterleaving sequences 132 are selected for the latch circuit modules 122 based on the tone number for the given modulation scheme. As described above, the bit deinterleaving sequence is selected for the corresponding modulation rate based on the tone number, where each tone number maps to one of a prescribed group of deinterleaving sequences (e.g., 132a, 132b, or 132c) via the deinterleaving sequence logic 130. Hence, the first four-bit output value 120 at event 184 would include the bits “38.0, 41.2, 45.1, and 48.0”, followed by the next four-bit output value at event 186 including the bits “51.2, 54.1, 58.0, 61.2”.
In addition, address selection for each successive group of code word fragments is controlled by the address selection logic 144 of
According to the disclosed embodiment, a multiple memory bank architecture enables data to be deinterleaved based on the writing of the code word fragments into memory, enabling addressing and deinterleaving logic to be implemented in a flexible manner that enables the deinterleaver module 84 to provide flexibility in deinterleaving different modulation rate data streams within the same architecture. Further, the serial input/parallel output scheme minimizes latency in the deinterleaving process, enabling the deinterleaved data to be output as soon as the first row of data has been stored. Moreover, total operation latency is reduced to less than one OFDM symbol length (160 clock cycles at 40 MHz) based on the overlapping of write and read operations, and cascaded bit deinterleaving. Hence, the output module 104 is configured for outputting the deinterleaved data for an entire code word, from the memory banks 100, within one OFDM symbol time 200 of reception of the interleaved data by the deinterleaver module.
While this invention has been described with what is presently considered to be the most practical preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
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