Patent Application
20220360117
The present disclosure relates generally to an electronic system and method, and, in particular embodiments, to a wireless power transfer system and method.
Wireless charging systems are becoming ubiquitous in today's society. For example, many smartphones and wearables implement wireless charging technology. Ease of use, greater reliability, spatial freedom, reduced connectors and openings, and the possibility of hermetically sealing are among the benefits offered by wireless charging. Wireless charging standards allow for interoperability between different devices and manufacturers. Some wireless charging standards, such as the Qi standard from the Wireless Power Consortium, and standards promoted by the AirFuel alliance, are becoming widely adopted. The Qi standard uses inductive charging operating between 80 kHz and 300 kHz to wirelessly transmit power from a transmitter to a receiver. Standards promoted by the AirFuel alliance use resonant wireless charging operating at 6.78 MHz to wirelessly transmit power from a transmitter to a receiver.
In accordance with an embodiment, a method for transmitting data from a wireless power receiver to a wireless power transmitter includes: wirelessly receiving power with a receiver resonant tank of the wireless power receiver from a transmitting coil of the wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce a rectified voltage; and while wirelessly receiving power with the receiver resonant tank, encoding data by causing transitions in a transmitter current flowing through the transmitting coil using the synchronous rectifier circuit, where encoding the data includes: applying a first sudden delay period in a first direction to a first switching of the first and second legs to cause a transition in the transmitter current; and after the first switching of the first and second legs, applying a first gradual delay in the first direction to subsequent switching of the first and second legs, where the first gradual delay is gradually incremented by a gradual increment period that is smaller than the first sudden delay period.
In accordance with an embodiment, a method for transmitting data from a wireless power receiver to a wireless power transmitter includes: wirelessly receiving power with a receiver resonant tank of the wireless power receiver from a transmitting coil of the wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce a rectified voltage, where the first leg includes first and second transistors, and where the second leg includes third and fourth transistors; and while wirelessly receiving power with the receiver resonant tank, encoding data by causing transitions in a transmitter current flowing through the transmitting coil using the synchronous rectifier circuit, where encoding the data includes: turning off the first, second, third and fourth transistors for a first sudden period during a first switching cycle of the first and second legs to cause a transition in the transmitter current; and after the first switching cycle, turning off the first, second, third and fourth transistors for a first gradual period during subsequent switching cycles of the first and second legs, where the first gradual period is gradually incremented by a gradual increment period that is smaller than the first sudden period.
In accordance with an embodiment, a method for regulating a rectified voltage includes: wirelessly receiving power with a receiver resonant tank of a wireless power receiver from a transmitting coil of a wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce the rectified voltage; and while wirelessly receiving power with the receiver resonant tank, adjusting a phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, to regulate the rectified voltage at a target voltage.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
The making and using of the embodiments disclosed are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to “an embodiment” in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as “in one embodiment” that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.
Embodiments of the present invention will be described in a specific context, a wireless power transfer system, method of operation, and method of in-band communication. Some embodiments may be implemented in wired power transfer systems. Some embodiments may comply with one or more wireless power transfer standard such as the Qi standard (e.g., versions 1.0, 1.1, 1.2, 1.2.3, 1.2.4).
It is understood that the term wireless charging is not limited to the charging of a battery, but includes wireless power transmission generally, unless stated otherwise.
Communication between a wireless power receiver (e.g., 104) and a wireless power transmitter (e.g., 102) is an important aspect of wireless power transfer. Conventional in-band communication between a wireless power receiver and a wireless power transmitter may be performed, e.g., by load modulation at 1 kHz to 2 kHz (e.g., by modulating the amount of power drawn from RX LC tank 108 by using capacitor bank 120 connected to the RX LC tank 108 or resistor 132 and switch 130 connected to the output of bridge 116, as shown in
A transition in current ITX for bit encoding purposes according to the bit encoding scheme illustrated in
Data may be transmitted using the bit encoding scheme illustrated in
In an embodiment of the present invention, a wireless power receiver communicates with a wireless power transmitter using in-band communication by performing load modulation with a synchronous rectifier circuit that is coupled to the RX LC tank. By performing the load modulation with the synchronous rectifier circuit, some embodiments advantageously avoid implementing a capacitor bank and/or a resistor for performing load modulation. Thus, some embodiments advantageously achieve a smaller footprint and/or lower costs compared to conventional solutions that rely on a capacitor bank and/or a resistor for load modulation. In some embodiments, the wireless power receiver performs the load modulation in accordance with the Qi standard (e.g., versions 1.0, 1.1, 1.2, 1.2.3, and 1.2.4, for example), thereby advantageously allowing for the reuse of a conventional wireless power transmitter without any hardware or software modifications.
As shown in
During normal operation, controller 210 controls transistors 206, 207, 208, and 209 to generate a current ITX having a frequency, e.g., between 80 kHz and 300 kHz, such as 127 kHz. The magnetic field generated by transmitting coil LTX as a result of the flow of current ITX induces current IRx to flow through LC tank 108. Voltage VRX generated across terminals of RX LC tank 108 is rectified by synchronous rectifier 216 to produce rectified voltage VRX_DC. Filtering capacitor 212 may be used to remove fluctuations of voltage VRX_DC at the switching (operating) frequency of the wireless power receiver (e.g., 100 kHz to 300 kHz).
In some embodiments, the rectified voltage VRX_DC is used to power load 228, e.g., via a DC/DC converter 214 followed by LDO 226.
In some embodiments, DC/DC converter 214 may be implemented as a boost, buck-boost, or buck converter. Other implementations, such as a fly-back converter, as well as capacitive charge-pump/voltage dividers may also be used. In some embodiments, DC/DC converter 214 may operate in a non-switching mode (e.g., in bypass mode) during periods of times during normal operation. In some embodiments, DC/DC converter 214 may be omitted. In some embodiments, LDO 228 may be omitted. In some embodiments, converter 214 and LDO 228 may be omitted.
Load 228 may be, e.g., a custom or general purpose microcontroller, a battery charger, or other electronic circuit, such as other digital, analog, or mixed signal circuit, such as amplifiers, power management circuits, audio circuits, etc. For example, in some embodiments, load 228 is a power converter, e.g., for powering other circuits.
LDO 226 may be implemented in any way known in the art, such as by using a regulation transistor to couple voltage V214 to voltage Vout, and an amplifier in a feedback network that senses output voltage Vout and controls the control terminal of the regulation transistor to provide a regulated output voltage Vout. Other implementations are possible.
In some embodiments, other converters may be used instead of, or in addition to LDO 226. For example, in some embodiments, a switching regulator may be used instead of LDO 226. In some embodiments, voltage V214 is provided directly to load 228 without an intervening power converter.
In some embodiments, controller 230 is used to control synchronous rectifier 216 to produce rectified voltage VRX_DC from voltage VRX. Controller 230 may be implemented, e.g., as a general purpose or custom microcontroller including combinatorial logic coupled to a memory. Other implementations are also possible.
In some embodiments, controller 210 is used to control driver 214. Controller 210 may be implemented, e.g., as a general purpose or custom microcontroller including combinatorial logic coupled to a memory. Other implementations are also possible.
In some embodiments, filtering capacitor 212 may have a capacitance of, e.g., 100 μF. Other capacitances, such as higher than 100 μF (e.g., 150 μF or more) or lower than 100 μF (e.g., 20 μF or less) may also be used.
During normal operation, as shown in
As shown in
In some embodiments, wireless power receiver 204 performs load modulation for in-band communication by adding and removing energy from filtering capacitor 212 using synchronous rectifier 216. In some embodiments, the load modulation for in-band communication is performed according to the bit encoding scheme illustrated in
In some embodiments, energy is added to filtering capacitor 212 or removed from filtering capacitor 212 by phase shifting the switching time of synchronous rectifier 216 with respect to current IRX. In some embodiments, energy is added to filtering capacitor 212 or removed from filtering capacitor 212 by phase shifting the switching time of the first/second leg with respect to the second/first leg. In some embodiments, phase shifting the switching of the first/second leg with respect to the second/first leg or with respect to the zero-crossing of current IRX advantageously causes an impedance change (as seen from wireless power transmitter 202), which causes a transition in current ITX. In some embodiments, the timing of such transitions can be monitored to receive data via TX LC tank 106. The received data may be decoded, e.g., with respect to a reference clock (e.g., available to wireless power transmitter 102). In some embodiments, the impedance, as seen from wireless power transmitter 202, is changed to cause transitions in current ITX by adjusting the magnitude of dead-times during synchronous rectification. In some embodiments, wireless power transmitter 202 reconstructs the reference clock (e.g., 142) in a known manner based on edges/zero crossings in the demodulated signal (e.g., current ITX after filtering).
In an embodiment, energy is added to filtering capacitor 212 or removed from filtering capacitor 212 by (e.g., monotonically) increasing delay times td with respect to current IRX in a first or second direction, respectively, over the data transmission period. For example,
Curve 302 shows current IRX corresponding to no delay being applied to the driving signals of synchronous rectifier 216 (e.g., with respect to curve 304). Curve 304 shows driving signal A for driving of transistors 217 and 220 for conventional synchronous rectification (with no delay being applied with respect to current IRX. Curve 306 shows driving signal A for driving transistor 217, and 220 for transmitting data in-band using switching delays between the first and second legs with respect to the zero-crossing of current IRX, according to an embodiment of the present invention. Driving signal Ā for driving transistors 218 and 219 has opposite phase as signal A.
As illustrated in
As shown by curve 306, delay td may be added in a first direction (e.g., positive delay) or in a second direction (e.g., negative delay). Adding positive delays td with respect to the zero-crossing of current IRX causes voltage on capacitor 212 to increase. Adding negative delays td with respect to the zero-crossing of current IRX causes voltage on capacitor 212 to decrease.
In some embodiments, adding (e.g., with respect to the zero crossing of current IRX or with respect to the last switching phase of synchronous rectifier circuit 216) a sudden positive delay (e.g., from 0 ns to 100 ns) or a sudden negative delay (e.g., from 0 ns to 100 ns) causes a transition (e.g., from a high/low level to a low/high level) in current ITX that may be used to encode data (e.g., in accordance to the bit encoding scheme illustrated in
In some embodiments, sudden delays td are applied at a frequency between 1 kHz and 2 kHz.
In some embodiments, once a sudden (e.g., positive or negative) delay td is applied (causing a transition in current ITX) the delay td for subsequent switching cycles of the first and second legs is gradually incremented in the same direction (e.g., at a constant rate) to avoid additional undesired transitions in current ITX (e.g., avoid transitions in current ITX higher than 15 mA in a 100 μs period or avoid a transition in voltage VTX that is higher than 200 mV in a 100 μs period). In some embodiments, the gradually incrementing the delay td after the application of a sudden delay td includes incrementing the delay td at a rate that is lower than 50% of the rate of the sudden delay td. For example, if a sudden delay td from 0 ns to 100 ns is applied in the first direction (positive delay), the gradually incrementing of the delay td includes that for the next switching cycles, the delay td is incremented in steps of 10 ns (e.g., 110 ns, 120 ns, 130 ns, etc.) until the next transition in current ITX is desired.
In some embodiments, the sudden delay td may include a delay step between 10 ns to 500 ns (where time td of the preceding switching was 10 ns and is 500 ns in the current switching). In some embodiments, the sudden delay td may have other magnitudes.
In some embodiments, the delay td is gradually adjusted during each switching transition of the first and second leg in the same direction (e.g., every other zero-crossing of current IRX. In some embodiments, the delay td is gradually adjusted during each switching transition of the first and second legs (e.g., every zero-crossing of current IRX. Other adjustment timings are also possible.
In some embodiments, avoiding additional undesired transitions may be achieved by incrementing the gradual delay td, after the sudden delay td, at a constant rate, and in the same direction as the sudden delay. In some embodiments, avoiding additional undesired transitions may be achieved by monitoring voltage VRX_DC and causing a gradual (e.g., monotonic, e.g., linear) change in (e.g., RMS, average) voltage VRX_DC (e.g., in the same direction as the change caused by the sudden delay), by dynamically adjusting the magnitude of the delay td. In some embodiments, controller 230 may receive an indication of the magnitude of voltage VRX_DC (e.g., via an ADC or analog circuit, such as using an op-amp, in a way known in the art) and may control the magnitude of the delay to cause the gradual change in voltage VRX_DC . Thus, in some embodiments, the RMS voltage of VRX_DC increases (e.g., linearly) from an initial voltage (e.g., corresponding to a voltage with immediately after application of the sudden delay td) to a higher voltage (e.g., until a time in which a next sudden transition in current ITX is caused). In some embodiments, the rate of change of voltage VRX_DC during the gradual change period is (e.g., constant and) less than 50% of the voltage change caused by the application of the sudden delay.
In an embodiment, energy is added to filtering capacitor 212 or removed from filtering capacitor 212 by (e.g., monotonically) increasing delay times tp between the first and second legs in a first or second direction, respectively, over the data transmission period. For example,
Curves 404 and 405 show driving signals A and Ā for driving transistors 217 and 218218, respectively, for conventional synchronous rectification (with no delay being applied with respect to current IRX). Curves 406 and 407 show driving signals B and
As illustrated in
As illustrated in
As shown by curves 409 and 410, delay tp may be added in a first direction (e.g., positive delay) or in a second direction (e.g., negative delay). Adding positive delays tp to the switching of the second leg with respect to the switching of the first leg causes voltage on capacitor 212 to increase. Adding negative delays tp to the switching of the second leg with respect to the switching of the first leg causes voltage on capacitor 212, thereby charging capacitor 212 to decrease. In some embodiments, depending on the operating point for the voltage/current phase shift, the phase shift between legs may cause inverted effects (e.g., the voltage on capacitor 212 may increase for negative changes in phase).
In some embodiments, adding a sudden positive delay (e.g., from 0 ns to 100 ns) or a sudden negative delay (e.g., from 0 ns to 100 ns) to the second leg with respect to the first leg causes a transition (e.g., from a high/low level to a low/high level) in current ITX that may be used to encode data (e.g., in accordance to the bit encoding scheme illustrated in
In some embodiments, sudden delays tp are applied at a frequency between 1 kHz and 2 kHz.
In some embodiments, once a sudden (e.g., positive or negative) delay tp is applied (causing a transition in current ITX) the delay tp for subsequent switching cycles of the first and second legs is gradually incremented in the same direction (e.g., at a constant rate) to avoid additional undesired transitions in current ITX (e.g., avoid transitions in current ITX higher than 15 mA in a 100 μs period or avoid a transition in voltage VTX that is higher than 200 mV in a 100 μs period). In some embodiments, the gradually incrementing the delay tp after the application of a sudden delay tp includes incrementing the delay at a rate that is lower than 50% of the rate of the sudden delay. For example, if a sudden delay from 0 ns to 100 ns is applied in the first direction (positive delay), the gradually incrementing of the delay tp may cause that for the next switching cycles, the delay is incremented in steps of 10 ns (e.g., 110 ns, 120 ns, 130 ns, etc.) until the next transition in current ITX is desired.
In some embodiments, the sudden delay tp may include a delay step between 10 ns to 500 ns (where time td of the preceding switching was 10 ns and is 500 ns in the current switching). In some embodiments, the sudden delay tp may have other magnitudes.
In some embodiments, the delay tp is gradually adjusted during each switching transition of the first and second leg in the same direction (e.g., every other zero-crossing of current IRX. In some embodiments, the delay tp is gradually adjusted during each switching transition of the first and second legs (e.g., every zero-crossing of current IRX). Other adjustment timings are also possible.
In some embodiments, avoiding additional undesired transitions may be achieved by incrementing the gradual delay tp, after the sudden delay tp, at a constant rate, and in the same direction as the sudden delay. In some embodiments, avoiding additional undesired transitions may be achieved by monitoring voltage VRX_DC and causing a gradual (e.g., monotonic, e.g., linear) change in (e.g., RMS, average) voltage VRX_DC (e.g., in the same direction as the change caused by the sudden delay), by dynamically adjusting the magnitude of the delay tp. In some embodiments, controller 230 may receive an indication of the magnitude of voltage VRX_DC (e.g., via an ADC or analog circuit, such as using an op-amp, in a way known in the art) and may control the magnitude of the delay to cause the gradual change in voltage VRX_DC . Thus, in some embodiments, the RMS voltage of VRX_DC increases (e.g., linearly) from an initial voltage (e.g., corresponding to a voltage with immediately after application of the sudden delay tp) to a higher voltage (e.g., until a time in which a next sudden transition in current ITX is caused). In some embodiments, the rate of change of voltage VRX_DC during the gradual change period is (e.g., constant and) less than 10% of the voltage change caused by the application of the sudden delay.
In some embodiments, after application of a sudden delay to the switching of the first and second legs (e.g., with respect to current IRX (td) or with respect to the other leg (tp)) voltage VRX_DC is at least VRX_DC_thres higher or at least VRX_DC_thres lower than before application of the sudden delay. In some embodiments, VRX_DC_thres is 5%. In some embodiments, VRX_DC_thres may be higher than 5%, such as 6%, 9% or more. In some embodiments, VRX_DC_thres may be lower than 5%, such as 4%, 2% or lower.
In an embodiment, transitions in current ITX for encoding data are caused changing the impedance seen by the wireless power transmitter by (e.g., monotonically) increasing or decreasing dead-times over the data transmission period. For example,
As shown in
In some embodiments, period th may be applied around the zero-crossing of current IRX. For example, in some embodiments, transistors 217, 218, 219, and 220 are turned off at the zero-crossing (or slightly before, or slightly after) of current IRX and remain off for the period th. In some embodiments, causing the dead-time to occur around the zero-crossing of current IRX advantageously allows for a change in operating mode of rectifier (from active rectification to passive rectification) while avoiding hard switching transistors 217, 218, 219, and 220.
In some embodiments, period th may be lower than 1 μs, such as, e.g., 50 ns. Other values are also possible.
In some embodiments, changing the duration of period th causes a change in impedance, as seen by wireless power transmitter 202. In some embodiments, applying a sudden change (e.g., increase or decrease) in period th (e.g., from 0 ns duration to 100 ns duration or from 100 ns duration to 50 ns duration) causes a transition (e.g., from a high/low level to a low/high level) in current ITX that may be used to encode data (e.g., in accordance to the bit encoding scheme illustrated in
In some embodiments, sudden changes in period th are applied at a frequency between 1 kHz and 2 kHz.
In some embodiments, once a sudden (e.g., increase or decrease) change in period th is applied (causing a transition in current ITX) the period th is gradually changed (e.g., increased/decreased) in the same direction (e.g., at a constant rate) to avoid additional undesired transitions in current ITX (e.g., avoid transitions in current ITX higher than 15 mA in a 100 μs period or avoid a transition in voltage VTX that is higher than 200 mV in a 100 μs period). In some embodiments, the gradual change in duration of period th after the application of a sudden change in duration of period th includes incrementing/decrementing the duration of period th at a rate that is lower than 50% of the rate of the sudden change in duration of period th. For example, if a sudden change in duration of period th involves increasing the duration of period th from 0 ns to 100 ns, the gradual incrementing of the period th may cause that for the next switching cycles, the duration of period th is incremented in steps of 10 ns (e.g., 110 ns, 120 ns, 130 ns, etc.) until the next transition in current ITX is desired. In some embodiments, modulation of period th causes a temporary drop in voltage in capacitor 212.
In some embodiments, the sudden change in period th may include a duration change between 100 ns to 50 ns. In some embodiments, the duration of the sudden change in period th may be lower than 50 ns or higher than 100 ns.
In some embodiments, avoiding additional undesired transitions may be achieved by changing the duration of period th, after the sudden change in duration of period th, at a constant rate, and in the same direction as the sudden change in duration of period th. In some embodiments, avoiding additional undesired transitions may be achieved by monitoring voltage VRX_DC and causing a gradual (e.g., monotonic, e.g., linear) change in (e.g., RMS) voltage VRX_DC (e.g., in the same direction as the change caused by the sudden delay), by dynamically adjusting the duration of period th. In some embodiments, controller 230 may receive an indication of the magnitude of voltage VRX_DC (e.g., via an ADC) and may control the duration of period th to cause the gradual change in voltage VRX_DC . Thus, in some embodiments, the RMS voltage of VRX_DC increases (e.g., linearly) from an initial voltage (e.g., corresponding to a voltage with immediately after application of the sudden delay) to a higher voltage (e.g., until a time in which a next sudden transition in current ITX is caused). In some embodiments, the rate of change of voltage VRX_DC during the gradual change period is (e.g., constant and) less than 10% of the voltage change caused by the application of the sudden delay.
In some embodiments, the data transmission rate is many times lower than the switching frequency of wireless power receiver 204, such as 40 times lower or more. For example, in an embodiment, the data transmission rate is 2 kHz and the switching frequency of wireless power receiver 204 is 127 kHz. Other frequencies may also be used.
Advantages of some embodiments include that, by using the synchronous rectifier circuit to cause sudden changes in the impedance (e.g., causing a sudden change in voltage VRX_DC), as seen by the wireless power transmitter, to cause an associated transition in current ITX, and by keeping constant the rate of change of the impedance (e.g., the rate of change in voltage VRX_DC) when transitions in current ITX are undesired, some embodiments advantageously encode data for a wireless power transmitter in compliance with the Qi standard (e.g., versions 1.0, 1.1, 1.2, 1.2.3, 1.2.4) without using a capacitor bank (e.g., 120) or resistor switching (e.g., 130, 132). Thus, some embodiments, advantageously allows for a conventional wireless power transmitter operating in accordance with the Qi standard (e.g., versions 1.0, 1.1, 1.2, 1.2.3, 1.2.4) to successfully demodulate the data transmitted by wireless power receiver 204, e.g., by using analog or digital filtering to extract data from the voltage across coil LTX, e.g., encoded using amplitude-shift keying (ASK), phase-shift-keying (PSK) or load modulation in general (combination of ASK and PSK).
During step 602, an RX LC tank (e.g., 108) of a wireless power receiver (e.g., 204) receives power from a transmitting coil LTX of a wireless power transmitter (e.g., 102, 202).
During step 604, while receiving power, the transistors (e.g., 217, 218, 219, and 220) are controlled so as to cause a transition in current ITX from a first level (e.g., low/high) to a second level (e.g., high/low) to encode data based on the time location of the transitions (e.g., in accordance with the bit encoding scheme illustrated in
During step 606, data is decoded by the wireless power transmitter by determining the location of transitions in current ITX or voltage VTX with respect to a clock signal (e.g., in accordance with the bit encoding scheme illustrated in
In some embodiments, the wireless power transmitter is a conventional wireless power transmitter complying with the Qi standard (e.g., versions 1.0, 1.1, 1.2, 1.2.3, 1.2.4). In some embodiments, the wireless power transmitter identifies a transition in current ITX when current ITX exhibits a change of at least 15 mA in a 100 μs period. In some embodiments, the wireless power transmitter identifies a transition in voltage VTX when voltage VTX exhibits a change of at least 200 mV in a 100 μs period.
During step 702, data transmission begins. In some embodiments, the data transmitted is encoded in bytes having 11 bits including a start event (e.g., a start bit of 0) followed by 8 bits, follows by a parity bit, followed by a stop event (e.g., a single bit of 1). In some embodiments, the data transmitted bytes are arranged in packets having a format including a preamble, followed by a header, followed by a message, and the followed by a checksum.
During step 704, a sudden switching delay (e.g., td or tp) is added to the switching of the first and/or second legs in a first (e.g., positive delay) or second (e.g., negative delay) direction with respect to the zero-crossing of current IRX or with respect to the other leg to cause a transition in current ITX.
During step 706, the switching delay is gradually increased in the same direction as the previously applied switching sudden delay. If during step 708 it is determined that additional transitions in current ITX are desired, e.g., to properly encode the data (e.g., in accordance with a selected encoding scheme), then step 704 is repeated. Otherwise, the data transmission ends.
In some embodiments, each time step 704 is performed during the same data transmission event, the direction of the sudden switching delay applied is toggled. For example, in some embodiments, a first sudden switching delay td (and/or tp) is applied (during step 704) that increases the delay from 0 ns to 50 ns. After gradually increasing (during step 706) the switching delay td (and/or tp) in a first direction up to a higher switching delay (e.g., 60 ns), a sudden switching delay td (and/or tp) in a second direction is applied. In some embodiments, the second sudden delay may cause a change in switching delay with respect to the zero-crossing of current IRX, e.g., from 60 ns delay to −50 ns delay (which then gradually increases to, e.g., −60 ns) until the next time step 604 is executed. In some embodiments, the second sudden delay may cause a change in switching delay with respect to the previous switching time, e.g., from 60 ns to 10 ns, and then gradually increasing in the same second direction up to a lower switching delay (e.g., −10 ns). In some embodiments, the delays in the first and second directions are symmetric. In some embodiments, the symmetric delays are centered at the zero-crossing of current IRX.
In some embodiments, step 704 is performed at a frequency between 1 kHz and 2 kHz.
Some embodiments may adjust delay time td with respect to zero-crossing of current IRX and not delay time tp between the first and second legs during steps 704 and 706. Some embodiments may adjust delay time t delay time tp between the first and second legs, and not adjust delay time td with respect to zero-crossing of current IRX during steps 704 and 706. Some embodiments may adjust both delay time td with respect to zero-crossing of current IRX and delay time tp between the first and second legs during steps 704 and 706.
During step 804, a sudden switching dead-time period (e.g., th) is applied in a first (e.g., increasing) or second (e.g., decreasing) direction. For example, in some embodiments, the sudden change in switching dead-time period causes all transistors to be off for a period of, e.g., 50 ns during each switching cycle (from 0 ns).
During step 806, the switching dead-time period is gradually changed (increased/decreased) in the same direction as the previously applied sudden switching dead-time period. For example, in some embodiments, if the sudden switching dead-time period increased from 0 ns to 50 ns, the gradual change during step 806 is a gradual increment of the switching dead-time period from 50 ns up to a higher dead-time period (e.g., 60 ns). In some embodiments, if the sudden switching dead-time period decreased from 60 ns to 30 ns, the gradual change during step 806 is a gradual decrease of the switching dead-time period from 30 ns up to a lower dead-time period (e.g., 20 ns).
In some embodiments, steps 704 and 804 may be performed during the same data transfer process. For example, a method for encoding data using synchronous rectifier 216 may include sequentially performing steps 702, 704, 706, 708, 804, 806, 708, 704, 706 , 708 , 704, 706, 708, 804, 806, 708, 804, 806, 708, . . . , 710.
In an embodiment of the present invention, a wireless power receiver (e.g., 204) regulates the rectified voltage (e.g., VRX_DC) by modulating the switching times of a synchronous rectifier (e.g., 216) coupled to the receiver LC tank (e.g., 108). In some embodiments, the timing of the switching of the first and second legs of the synchronous rectifier is modulated with respect to a zero-crossing of a rectifier current (IRX) flowing through the receiver LC tank (e.g., as illustrated in
By regulating the rectified voltage using the synchronous rectifier, some embodiments advantageously achieve fast and improved load transient response, e.g., when the load (e.g., 228) suddenly changes. In some embodiments, such fast load transient response may occur before the wireless power transmitter (e.g., 202) has adjust the power transmitted in response to data received from the wireless power receiver (e.g., 204) via in-band communication. In some embodiments, the regulation of the rectified voltage is only active (e.g., actively modulating the switching times of the synchronous rectifier) during load transient, and becomes inactive (no switching time delays with respect to a switching time of a conventional synchronous rectifier) once the wireless power transmitter adjusts the transmitted power.
In some embodiments, wireless power receiver 204 regulates the rectified voltage VRX_DC by removing or adding energy to capacitor 212 using synchronous rectifier 216. For example, in some embodiments, adding a fixed positive delay time td over a plurality of switching cycles of synchronous rectifier 216 causes voltage VRX_DC to settle into a new voltage higher than without applying the fixed positive delay (as can be seen from
In some embodiments, adding a fixed negative delay time td over a plurality of switching cycles of synchronous rectifier 216 causes voltage VRX_DC to settle into a new voltage lower than without applying the fixed negative delay (as can be seen from
Some embodiments may regulate voltage VRX_DC to a target voltage by applying positive and negative delays (td) to the switching of the first and second legs with respect to the zero-crossing of current IRX.
As shown in
As illustrated by
Some embodiments may regulate voltage VRX_DC to a target voltage by applying positive and negative delays (tp) between the first and second legs of synchronous rectifier 216.
As shown in
As can be seen from
As shown in
As can be seen from
As shown in
As can be seen from
As shown in
As illustrated by
In some embodiments, regulating voltage VRX_DC to a target voltage using synchronous rectifier 216 advantageously allows for avoiding voltage spikes during a load transient event, thus advantageously protecting the circuit(s) (e.g., converter 214 and/or LDO 226) coupled to the output of synchronous rectifier 216 and/or protecting transistors 217, 218, 219, and/or 220 for damage or malfunctions caused by the overvoltage event. For example, when a load transient occurs, such as when the current consumed by load 228 suddenly decreases), voltage VRX_DC may increase as a result. In some embodiments, changing the phase angle between the switching of the first and second legs with respect to current IRX or with respect to each other, to apply a gain lower than 1 (e.g., by applying a negative delay td or negative delay tp) may cause voltage VRX_DC to remain at the target voltage (e.g., 20 V). In some embodiments, the response time to a load transient event is less than 2 ms , such as within 10 switching cycles or 100 μs.
In some embodiments, synchronous rectifier 216 continuously regulates voltage
VRX_DC to a target voltage. By continuously regulating voltage VRX_DC to a target voltage, some embodiments advantageous achieve lower voltage spikes as a result of a transient event and/or voltage spikes of shorter duration. In some embodiments, when the synchronous rectifier operates at a phase angle that is higher than a positive threshold or lower than a negative threshold, wireless power receiver 204 transmit a request to wireless power transmitter 202 to change the transmitted power to a level so that the phase angle can return to a level closer to 0 (e.g., between the negative threshold and the positive threshold). For example, when the phase angle is lower than −21.6 degrees, decreasing the transmitted power may cause the phase angle to increase towards 0 degrees, which may advantageously increase efficiency.
In some embodiments, regulation of voltage VRX_DC to a target voltage is activated upon detection of a load transient event. For example, in some embodiments, a comparator is used to detect a load transient event when voltage VRX_DC increases, e.g., by more than 5% (e.g., higher than 21 V for a 20 V target). As a result of the detection (e.g., when the output of the comparator is asserted), synchronous rectifier 216 modulates the switching time of the first and second legs with respect to current IRX to cause voltage VRX_DC to return and remain at the target voltage (e.g., 20 V). In some embodiments, the time between load transient detection until voltage VRX_DC is regulated at the target voltage is less than 2 ms. In some embodiments, wireless power receiver 204 transmit a request to wireless power transmitter 202 to lower the transmitted power. Once wireless power transmitter 202 lowers the power to a new level, synchronous rectifier 216 stops regulating voltage VRX_DC and returns to synchronous rectification with a phase angle of 0.
During step 1302, the power level PTX transmitted by a wireless power transmitter (e.g., 102, 202) is negotiated. For example, in some embodiments the power negotiation is performed between the wireless power transmitter and a wireless power receiver (e.g., 204) using in-band communication in accordance with the Qi standard (e.g., version 1.2.3).
In some embodiments, the in-band communication used for power negotiation is performed using a synchronous rectifier (e.g., 216) of the wireless power receiver (e.g., using methods 600, 700, or 800). In some embodiments, the in-band communication used for power negotiation is performed using a capacitor bank (e.g., 120) in a conventional manner.
In some embodiments, after the power negotiation ends, the synchronous rectifier produces, for the loading present during the power negotiation (e.g., load 228) the rectified voltage VRX_DC at the target voltage (e.g., 20 V) when switching the first and second legs at the zero-crossing of the receiver current IRX (delay td=0, and delay tp=0).
As the load changes, the synchronous rectifier changes during step 1304 the phase angle between the switching of the first and second legs with respect to current IRX or the phase angle between the switching of the first and second leg to adjust the gain (e.g., increase or decrease) to maintain voltage VRX_DC at the target voltage. In some embodiments, a controller (e.g., controller 230) controls the switching timing of the synchronous rectifier so as to adjust the phase angle.
When the phase angle is within a predefined phase angle range (e.g., between θl and θh), the synchronous rectifier continues to adjust the phase angle to regulate voltage VRX_DC, as illustrated by step 1306. If it is determined during step 1306 that the phase angle is outside the predefined phase angle range, then the wireless power receiver requests the wireless power transmitter during step 1308 to change the transmitted power PTX (e.g., using in-band communication). In some embodiments, after the request for changing the transmitter power PTX is processed and acknowledged by the wireless power transmitter, the synchronous rectifier produces, for the loading present at the time the request is made, the rectified voltage VRX_DC at the target voltage (e.g., 20 V) when switching the first and second legs at the zero-crossing of the receiver current IRX (delay td=0, and delay tp=0).
In some embodiments, this between θl and −5° and −30° (e.g., such as −10°) and θh is between 5° and 30° (e.g., such as 5°). Other values for θ1 and θh may also be used.
During step 1402, the synchronous rectifier operates by switching the first and second legs at the zero-crossing of the receiver current IRX (delay td=0, and delay tp=0). In some embodiments, when the loading of the synchronous rectifier during step 1402 is the same as the loading of the synchronous rectifier during step 1302, the synchronous rectifier produces the rectified voltage VRX_DC at the target voltage (e.g., 20 V).
As the load changes, the rectified voltage VRX_DC varies. When the rectified voltage VRX_DC is within a predefined voltage range (e.g., between Vl and Vh), the synchronous rectifier continues switch the first and second legs at the zero-crossing of the receiver current IRX (delay td=0, and delay tp=0), as illustrated by step 1404. In some embodiments, the rectified voltage VRX_DC is monitored/measured/determined by using a circuit (e.g., an ADC, or comparator) coupled to the output of the synchronous rectified (e.g., directly, via a voltage divider, or in other ways) in a known manner.
If it is determined during step 1404 that the rectified voltage is outside the predefined voltage range, then the synchronous rectifier regulates the rectified voltage VRX_DC to the target voltage during step 1304 by adjusting the phase angle, and requests a change in transmitted power PTX during step 1308.
In some embodiments, after the request for changing the transmitter power PTX is processed and acknowledged by the wireless power transmitter, the synchronous rectifier produces, for the loading present at the time the request is made, the rectified voltage VRX_DC at the target voltage (e.g., 20 V) when switching the first and second legs at the zero-crossing of the receiver current IRX (delay td=0, and delay tp=0), and step 1402 is performed.
As illustrated in
As shown in
As shown in
In some embodiments, the first feedback loop is more than an order of magnitude faster (or even more than two orders of magnitude faster) than the second loop. Thus, some embodiments, are advantageously capable of reacting in a fast manner (e.g., within 2 ms ) to a load transient, thus advantageously reducing the ripple, overshoot, and/or undershoot of rectified voltage VRX_DC .
By reacting in a fast manner to a load transient, some embodiments advantageously protect circuits coupled to the output of the synchronous rectified from overvoltage conditions without using an additional overvoltage protection circuit. Additional advantages of some embodiments include maintaining an input voltage within the specification to a power converter (e.g., 214, 226) so as to keep a steady voltage delivered to the load (e.g., 228) despite a temporary or permanent change in the current consumed by the load.
In some embodiments, such as some embodiments that implement LDO 226, reacting in a fast manner to a load transient advantageously results in less power (and less heat) being dissipated by the LDO as a result of an increase the in voltage VRX_DC .
In some embodiments, operating the second loop advantageously allows the synchronous rectifier to operate with a phase angle at or near 0 while still generating the rectified voltage VRX_DC at the target voltage. Thus, some embodiments advantageously generate the rectified voltage VRX_DC at the target voltage while operating at or near maximum wireless power transmission efficiency.
Advantages of some embodiments include regulating the rectified voltage VRX_DC and reacting to load transients in a fast manner (e.g., in less than 2 ms ) by operating the synchronous rectified with a phase angle (with respect to current IRX or between the first and second legs) different than 0 for shorts period of times (e.g., less than 1 second) while operating at or near maximum wireless power transfer efficiency by switching the first and second legs at the zero-crossing of current IRX for most of the time.
In some embodiments, the wireless power transmitter 202 may detect a change in impedance, as seen from the wireless power transmitter 202, resulting from the adjustment of the phase angle (e.g., during step 1304), and, in response, may adjust the level of wireless power transmitted PTX. For example, when load current ILOAD increases, the phase angle is increased during step 304 (e.g., by increasing the positive delay td or tp) to regulate the rectified voltage VRX_DC to the target voltage. The increase in the phase angle of the switching of the first and second legs causes an impedance change that causes an increase in the transmitter current ITX flowing through the LC tank 106. Similarly, when load current ILOAD decreases, the phase angle is decreased during step 304 (e.g., by increasing the negative delay td or tp) to regulate the rectified voltage VRX_DC to the target voltage. The decrease in the phase angle of the switching of the first and second legs causes an impedance change that causes a decrease in the transmitter current ITX. Thus, in some embodiments, the wireless power transmitter (e.g., 202) regulates the transmitter current ITX to a target (e.g., peak, or RMS) transmitter current to adjust the level of transmitted power PTX (e.g., before receiving a request to adjust the level of transmitted power PTX via, e.g., in-band communication).
In some embodiments, adjusting the phase angle of the synchronous rectifier 216 during step 1304 may cause a change in (e.g., peak or RMS value of) transmitter current ITX. In some embodiments, the wireless power transmitter may detect the change in transmitter current ITX and may regulate the transmitter current ITX so that it remains in the same level. For example,
During step 1702, a wireless power transmitter (e.g., 202) measures and stores (e.g., in a memory of the wireless power transmitter) a level (e.g., peak or RMS) of the transmitter current ITX. The level of the transmitter current ITX determined during step 1702 may be referred to as a transmitter calibration current, or as a transmitter target current.
Step 1702 may be performed when the synchronous rectifier (e.g., 216) of the wireless power receiver (e.g., 204) is switching at the zero-crossing of the receiver current IRX (e.g., when td=tp=0). For example, step 1702 may be performed during 1402. In some embodiments, method 1300 may include step 1402 between steps 1302 and 1304, e.g., for a limited period of time (e.g., less than 1 second) during which step 1702 is performed.
The wireless power transmitter may measure the transmitter current ITX in any way known in the art, such as based on a voltage across transistors 206, 207, 208, and/or 209, based on a voltage across a sense resistor through with current ITX (or a current based on current ITX flows), or in any other way known in the art.
During step 1704, the wireless power transmitter regulates the current ITX so that it is at the level of the transmitter target current.
In some embodiments, a request for changing the level of transmitted power PTX is received during step 1706. Such request may be sent by the wireless power receiver (e.g., during step 1308) and may be performed, e.g., in accordance with the Qi standard (e.g., version 1.2.3).
In some embodiments, when a request for changing the level of transmitted power PTX is received during step 1706, the wireless power transmitter may perform step 1702 once the new level of transmitted power is settled.
As shown in
In some embodiments, changes to delay time td or tp (e.g., for voltage regulation purposes) are made at a frequency selected so as to not interfere with in-band communication (where the in-band frequency range may be, e.g., between 1 kHz and 2 kHz). For example, in some embodiments, changes to delay time td or tp for voltage regulation purposes may be performed at a frequency lower than 1 kHz, such as 100 Hz or lower or at a frequency of 10 kHz, or higher.
In some embodiments, wireless power receiver 204 performs voltage regulation of VRX_DC by modulating the delay time td and/or tp simultaneously with in-band communication. For example, in some embodiments, the sudden and gradual increase in delay times (e.g., as performed in steps 704, 706, 804, and 806) are performed with respect to the fixed delay times (e.g., tp and/or td) used for regulating the rectified voltage VRX_DC (e.g., during step 1304).
In some embodiments, the switching times of the first and second legs of synchronous rectifier 216 are based on the receiver current IRX. For example, in some embodiments, synchronous rectifier 216 (or associated controller 230) determines when to switch transistors 217, 218, 219, and 220 (either before, after or at the zero-crossing of current IRX) based on detecting the zero-crossing current IRX . For example, in some embodiments, the next transistor that is to be turned off, e.g., based on the synchronous rectification sequence (such as shown by curve 304 of
In some embodiments, the switching of the first and second legs are both determined based on the zero-crossing of current IRX, such as when applying positive delays td or negative delays td. In some embodiments, the switching of one leg (e.g., the first leg) of the synchronous rectifier 216 is determined based on the zero-crossing of current IRX such that it switches, e.g., at the zero crossing, while the switching of the other leg (e.g., the second leg) is determined with respect to the switching of the first leg, such as when applying positive delays tp or negative delays tp.
In an embodiment of the present invention, a phase-locked loop (PLL) is used to control the switching of a synchronous rectifier coupled to the RX LC tank, or as reference signal in which to base the timing of the switching of the first and second legs of the synchronous rectifier. An oscillating signal based on zero-crossing detection and forward diode conduction detection of a transistor of the synchronous rectifier 216 is used as a reference signal for the PLL. In some embodiments, using a PLL for controlling the synchronous rectifier advantageously improves the accuracy of the switching times of the synchronous rectifier, which may be corrupted based on noisy measurements for zero-crossing and forward diode conduction detections.
Curves 1852 and 1854 illustrate signals A and A′, respectively, of an embodiment in steady state.
During normal operation, zero-crossing detector 1816 detects the zero-crossings of current IRX, and resets flip-flop 1810 when current IRX is at the zero-crossing (e.g., when current flowing through the current path of transistor 220 is below a predetermined threshold Vith). Forward diode conduction detector 1812 detects when transistor 220 is in forward diode conduction mode and sets flip-flop 1810 when transistor 220 is in forward diode conduction mode (e.g., when the drain voltage of transistor 220 is lower than the source voltage of transistor 220).
In some embodiments, signal A′ produced by flip-flop 1810 is equal to curve 304 (e.g., in steady state).
Signal A′ is used as a reference signal for PLL 1802, which then produces signal A for driving synchronous rectifier 216, as shown by curve 1852. For example, in some embodiments, phase comparator 1804 produces voltage Vpd, which is proportional to the phase different between signal A and signal A′. Voltage Vpd is then low-pass filtered to produce filtered voltage Vfpd, which controls VCO 1808. PLL 1802 operates to minimize the frequency and phase error between A and A′, e.g., in a known manner. Thus, in some embodiments, in steady state, the output A of PLL 1802 and signal A′ may be equal.
In some embodiments, the output of PLL 1802 (e.g., signal A at the output of PLL 1802) is used to drive synchronous rectifier 216. In some embodiments, the output of PLL 1802 is used as a reference signal, and controller 1830 controls the switching of transistors 217, 218, 219, and 220, e.g., to switch with delay td with respect to the output of PLL 1802. In some embodiments, the output of PLL 1802 is used as a reference signal, and controller 1830 controls the switching of one leg (e.g., transistors 217, 218) based on the output of PLL 1802, and controls the switching of the other leg (e.g., transistors 219, 220) to switch with delay tp with respect to the switching of the one leg and/or with respect to the output of PLL 1802.
In some embodiments, using PLL 1802 advantageously allows for proper driving of synchronous rectifier 216 when failing to detect or improperly detecting a zero-crossing and/or a forward diode conduction events (e.g., since low-pass filter 506 may filter such corrupted detection, leaving signal A unaffected). Additional advantages of some embodiments include driving synchronous rectifier 216 with low jitter and increased wireless power transfer efficiency.
Zero-crossing detector 1816 may be implemented, e.g., using amplifier 1818 followed by comparator 1820 to compare the voltage drop across transistor 220 (e.g., when transistor 220 is on) with a reference value, (e.g., since such voltage drop is proportional to the current flowing through transistor 220 times the rdson resistance of transistor 220). Other implementations for sensing zero-crossing events, such as using an ADC, are also possible.
Forward diode conduction detector 1812 may be implemented, e.g., using comparator 1814 to compare the drain and source voltages of transistor 220 (when transistor 220 is off) to produce an indication when the drain voltage is lower than the source voltage. Other implementations are also possible.
Although
In some embodiments, PLL 1802 is implemented as shown in
In some embodiments, controller 1830 may implement PLL 1802, e.g., digitally. For example, in some embodiments, circuits 1812, 816 and 1810 may be replaced by an ADC followed by digital circuits to implement zero-crossing detection and forward diode conduction detection. For example, in some embodiments, controller 1830 may be implemented, e.g., as a general purpose or custom microcontroller including combinatorial logic coupled to a memory.
In some embodiments, controller 1830 may implement, e.g., additionally, the functionality of controller 1830, such as for performing in-band communication, for controlling converter 214, and/or for performing VRX_DC voltage regulation. For example, in some embodiments, the output of PLL 1802 may be used as a reference by controller 1830 for controlling transistors 217, 218, 219, and 220, and controller 1830 may modify the switching of transistors 217, 218, 219, and 220 (e.g., instead of following the output of PLL 1802 exactly) to introduce delays td, delay tp, and/or period th.
In some embodiments, wireless power transmitter 202 may change the operating frequency of TX LC tank 106, thus affecting the operating frequency of RX LC tank 108. If a PLL, such as PLL 1802, is used to drive synchronous rectifier 216, the signal A at the output of PLL 1802 may be out of synch with current IRX. As a result of signal A being out of synch with current IRX, the detection window for performing zero-crossing detection and forward diode conduction detection may occur far from the zero-crossing of current IRX. Thus, signal A′ may be corrupted (e.g., stuck at a particular state or switching at a frequency different than the frequency of current IRX).
In some embodiments, when the PLL (e.g., 1802) loses synchronization with the received reference signal (e.g., A′), the duty cycle of the synchronous rectifier (e.g., 216) is (e.g., incrementally) reduced, while being driven based on the output of the PLL, to (e.g., incrementally) increase the dead-time for detecting the zero-crossings and forward diode conduction of a transistor (e.g., 220) of the synchronous rectifier, to, e.g., facilitate the locking of the PLL to the new frequency and phase.
In an embodiment, transistor 220 is off during a dead-time that spans from before transistor 220 is expected to switch until after transistor 220 is expected to switch. The dead-time, thus, allows for proper measurement of forward diode conduction of transistor 220 (since, detector 1812 is capable of detecting forward diode conduction when transistor 220 is off).
For example, in some embodiments, the dead-time during steady state (where the output of PLL 1802 and signal A′ are locked) may be, e.g., less than 20% of the switching period, such as less than 10%, or lower. As a non-limiting example,
As illustrated by
Example embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein.
Example 1. A method for transmitting data from a wireless power receiver to a wireless power transmitter, the method including: wirelessly receiving power with a receiver resonant tank of the wireless power receiver from a transmitting coil of the wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce a rectified voltage; and while wirelessly receiving power with the receiver resonant tank, encoding data by causing transitions in a transmitter current flowing through the transmitting coil using the synchronous rectifier circuit, where encoding the data includes: applying a first sudden delay period in a first direction to a first switching of the first and second legs to cause a transition in the transmitter current; and after the first switching of the first and second legs, applying a first gradual delay in the first direction to subsequent switching of the first and second legs, where the first gradual delay is gradually incremented by a gradual increment period that is smaller than the first sudden delay period.
Example 2. The method of example 1, where the transition of the transmitter current includes a change of at least 15 mA in a 100 μs period.
Example 3. The method of one of examples 1 or 2, where the first sudden delay period is a time period between 10 ns and 500 ns.
Example 4. The method of one of examples 1 to 3, where the wireless power receiver does not have a capacitor bank connected to an intermediate node, the intermediate node coupled between the receiver resonant tank and the synchronous rectifier circuit.
Example 5. The method of one of examples 1 to 4, where the first leg includes first and second transistors, where the second leg includes third and fourth transistors, and where switching the first and second legs includes: when the first and third transistors are on and the second and fourth transistors are off, turning off the first and third transistors and turning on the second and fourth transistors during a zero-crossing of the receiver current; and when the second and fourth transistors are on and the first and third transistors are off, turning off the second and fourth transistors and turning on the first and third transistors during a zero-crossing of the receiver current.
Example 6. The method of one of examples 1 to 5, where the gradual increment period is constant.
Example 7. The method of one of examples 1 to 6, where the gradual increment period is based on the rectified voltage.
Example 8. The method of one of examples 1 to 7, where applying the first gradual delay in the first direction to subsequent switching of the first and second legs causes a root-mean-square (RMS) value of the rectified voltage to change at a constant rate.
Example 9. The method of one of examples 1 to 8, where applying the first sudden delay period in the first direction includes delaying the switching of the first and second legs with respect to the receiver current.
Example 10. The method of one of examples 1 to 9, where applying the first sudden delay period in the first direction includes advancing the switching of the first and second legs with respect to the receiver current.
Example 11. The method of one of examples 1 to 10, where applying the first sudden delay period in the first direction includes delaying the switching of the second leg with respect to the first leg.
Example 12. The method of one of examples 1 to 11, where applying the first sudden delay period in the first direction includes advancing the switching of the second leg with respect to the first leg.
Example 13. The method of one of examples 1 to 12, where the first switching is associated with a start bit of a data packet to be transmitted from the wireless power receiver to the wireless power transmitter.
Example 14. The method of one of examples 1 to 13, where the start bit of the data packet is a first bit of a preamble of a data packet.
Example 15. The method of one of examples 1 to 14, where encoding the data includes encoding the data in accordance with Qi standard.
Example 16. The method of one of examples 1 to 15, where encoding the data further includes: applying a second sudden delay period in a second direction to a further switching of the first and second legs to cause a further transition in the transmitter current, the second direction being opposite the first direction; and after the further switching of the first and second legs, applying a second delay in the second direction to subsequent switching of the first and second legs, where the second delay is gradually incremented by a second gradual increment period that is smaller than the second sudden delay period.
Example 17. The method of one of examples 1 to 16, where encoding the data further includes alternating application of the first sudden delay period and the second sudden delay period while switching first and second legs during a data transmission period.
Example 18. The method of one of examples 1 to 17, where causing transitions in the transmitter current includes causing transitions in the transmitter current at a frequency between 1 kHz and 2 kHz.
Example 19. A method for transmitting data from a wireless power receiver to a wireless power transmitter, the method including: wirelessly receiving power with a receiver resonant tank of the wireless power receiver from a transmitting coil of the wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce a rectified voltage, where the first leg includes first and second transistors, and where the second leg includes third and fourth transistors; and while wirelessly receiving power with the receiver resonant tank, encoding data by causing transitions in a transmitter current flowing through the transmitting coil using the synchronous rectifier circuit, where encoding the data includes: turning off the first, second, third and fourth transistors for a first sudden period during a first switching cycle of the first and second legs to cause a transition in the transmitter current; and after the first switching cycle, turning off the first, second, third and fourth transistors for a first gradual period during subsequent switching cycles of the first and second legs, where the first gradual period is gradually incremented by a gradual increment period that is smaller than the first sudden period.
Example 20. The method of example 19, where the transition of the transmitter current includes a change of at least 15 mA in a 100 μs period.
Example 21. The method of one of examples 19 or 20, where the first sudden period is a time period between 10 ns and 500 ns.
Example 22. The method of one of examples 19 to 21, where the wireless power receiver does not have a capacitor bank connected to an intermediate node, the intermediate node coupled between the receiver resonant tank and the synchronous rectifier circuit.
Example 23. The method of one of examples 19 to 22, where switching the first and second legs includes: when the first and third transistors are on and the second and fourth transistors are off, turning off the first and third transistors and turning on the second and fourth transistors during a zero-crossing of a receiver current flowing through the receiver resonant tank; and when the second and fourth transistors are on and the first and third transistors are off, turning off the second and fourth transistors and turning on the first and third transistors during a zero-crossing of the receiver current.
Example 24. The method of one of examples 19 to 23, where the gradual increment period is constant.
Example 25. The method of one of examples 19 to 24, where the gradual increment period is based on the rectified voltage.
Example 26. The method of one of examples 19 to 25, where turning off the first, second, third and fourth transistors for the first gradual period during subsequent switching cycles of the first and second legs causes a root-mean-square (RMS) value of the rectified voltage to change at a constant rate.
Example 27. The method of one of examples 19 to 26, where the first switching cycle is associated with a start bit of a data byte to be transmitted from the wireless power receiver to the wireless power transmitter.
Example 28. The method of one of examples 19 to 27, where encoding the data includes encoding the data in accordance with Qi standard.
Example 29. The method of one of examples 19 to 28, where causing transitions in the transmitter current includes causing transitions in the transmitter current at a frequency between 1 kHz and 2 kHz.
Example 30. The method of one of examples 19 to 29, where a zero-crossing of the receiver current occurs during the first sudden period.
Example 31. The method of one of examples 19 to 30, where a peak of the receiver current occurs during the first sudden period.
Example 32. A method for regulating a rectified voltage, the method including: wirelessly receiving power with a receiver resonant tank of a wireless power receiver from a transmitting coil of a wireless power transmitter; rectifying a receiver voltage received from the receiver resonant tank by switching first and second legs of a synchronous rectifier circuit based on a zero-crossing of a receiver current flowing through the receiver resonant tank to produce the rectified voltage; and while wirelessly receiving power with the receiver resonant tank, adjusting a phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, to regulate the rectified voltage at a target voltage.
Example 33. The method of example 32, where adjusting the phase angle includes: when the rectified voltage is below the target voltage, increasing the phase angle between the first and second legs and the zero-crossing of the receiver current to increase the rectified voltage towards the target voltage; and when the rectified voltage is above the target voltage, decreasing the phase angle between the first and second legs and the zero-crossing of the receiver current to decrease the rectified voltage towards the target voltage.
Example 34. The method of one of examples 32 or 33, where adjusting the phase angle includes: when the rectified voltage is below the target voltage, increasing the phase angle between the first and second legs to increase the rectified voltage towards the target voltage; and when the rectified voltage is above the target voltage, decreasing the phase angle between the first and second legs to decrease the rectified voltage towards the target voltage.
Example 35. The method of one of examples 32 to 34, where adjusting the phase angle includes adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, in a range that is between −30° and 30°.
Example 36. The method of one of examples 32 to 35, further including, when the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, is above a first predetermined phase angle or below a second predetermined phase angle, transmitting a request to the wireless power transmitter to change a level of transmitted power.
Example 37. The method of one of examples 32 to 36, where the first predetermined phase angle is between −5° and 30°, and where the second predetermined phase angle is between 5° and 30°.
Example 38. The method of one of examples 32 to 37, where transmitting the request to the wireless power transmitter includes transmitting the request via the receiver resonant tank.
Example 39. The method of one of examples 32 to 38, further including negotiating, between the wireless power receiver and the wireless power transmitter, a level of transmitted power, where adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, to regulate the rectified voltage at the target voltage is performed after the negotiation.
Example 40. The method of one of examples 32 to 39, further including, after the negotiation and before adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, switching, for a first period of time, the first and second legs with a phase angle of zero between the first and second legs and the zero-crossing of the receiver current, and with a phase angle of zero between the first and second legs.
Example 41. The method of one of examples 32 to 40, where the first period of time is less than 1 second.
Example 42. The method of one of examples 32 to 41, where the first period of time is determined based on the rectified voltage.
Example 43. The method of one of examples 32 to 42, where adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, to regulate the rectified voltage at a target voltage includes adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, when the rectified voltage is above a first predetermined voltage or below a second predetermined voltage.
Example 44. The method of one of examples 32 to 43, further including, when the rectified voltage is above a first predetermined voltage or below a second predetermined voltage, transmitting a request to the wireless power transmitter to change a level of transmitted power.
Example 45. The method of one of examples 32 to 44, further including regulating a transmitter current flowing through the transmitting coil to a target current.
Example 46. The method of one of examples 32 to 45, further including, determining the target current based on the transmitter current flowing through the transmitting coil when the first and second legs are switching with a phase angle of zero with respect to each other and with a phase angle of zero with respect to the zero-crossing of the receiver current.
Example 47. The method of one of examples 32 to 46, further including begin regulating the transmitter current when the transmitter current is below a first current threshold or above a second current threshold.
Example 48. The method of one of examples 32 to 47, further including generating a reference timing signal with a phase-locked loop (PLL) coupled to the synchronous rectifier circuit, and where switching the first and second legs includes switching the first and second legs based on an output of the PLL.
Example 49. The method of one of examples 32 to 48, further including: detecting, with a forward diode conduction detector, when a given transistor of the first or second leg is in forward diode conduction mode; detecting, with a zero-crossing detector, a zero-crossing of the receiver current; and controlling the PLL based on an output of the forward diode conduction detector and based on an output of the zero-crossing detector.
Example 50. The method of one of examples 32 to 49, where a flip-flop has a first input coupled to the output of the forward diode conduction detector, a second input coupled to the output of the zero-crossing detector, and an output coupled to the PLL.
Example 51. The method of one of examples 32 to 50, where adjusting the phase angle between the first and second legs and the zero-crossing of the receiver current, or between the first and second legs, includes adjusting the phase angle of a switching of one leg of the first and second legs with respect to the output of the PLL.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
This application claims the benefit of U.S. Provisional Application No. 63/184,666, filed on May 5, 2021, which application is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63184666 | May 2021 | US |
