Wireless receiver apparatus and method

Abstract

Embodiments of the invention include a wakeup receiver (WRX) featuring a charge-domain analog front end (AFE) with parallel radio frequency (RF) rectifier, charge-transfer summation amplifier (CTSA), and successive approximation analog-to-digital converter (SAR ADC) stages. The WRX operates at very low power and exhibits above-average sensitivity, random pulsed interferer rejections, and yield over process.

Description

FIELD OF THE INVENTION

The invention is in the field of low-power sensor networks such as those that facilitate the internet of things (IoT).

BACKGROUND

Networks of wireless sensor nodes have become ubiquitous in the internet of things (IoT). As the technologies related to IoT evolve, the main goals for development of components include improved (reduced) power consumption, increased speed/higher data rate, better sensitivity, and robustness.

Ultra low power (ULP) receivers are gaining traction in various consumer and industrial markets as new standards are being defined to support them in IoT devices. Communication standards such as WiFi 802.11ba, BLE, and NB-IoT are all considering operating modes and signaling that take advantage of ULP receivers as companion radios for several reasons. They significantly reduce active and average power while providing continuous connectivity, thus enabling batteryless operation. They also simplify provisioning of new nodes, reduce synchronization energy overhead and latency to nearly zero, scale to networks of 1000s of nodes, and enable microsecond (ms) wakeup latency. ULP receivers have been demonstrated with better than −100 dBm sensitivity and 10 nW, but none have addressed aspects for widespread adoption such as selectivity, random pulsed interferer rejection, yield over process, voltage and temperature (PVT) variations, and security against replay or energy attacks.

A key component of wireless sensor networks are sensor nodes, which include main circuit components such as wakeup receivers (WRXs). Because of the nature of the network, these receivers are typically ULP receivers. Most IoT networks comprise many ULP receivers that are tasked with receiving radio frequency (RF) wireless signals over the air (OTA) and taking some local action based on the ULP receiver's interpretation of the received RF signals. Translating the received RF signal into a local action typically involves translating the continuous RF signal to some discrete “on/off” (e.g., Wakeup) type of message to a local component of the IoT system.

Current sensor nodes may have some low power characteristics. For example, certain ULP receive frontends that feature continuous-time analog circuitry do consume a relatively low amount of power. But they exhibit low sensitivity, and poor robustness in the presence of interference and across wide temperature range.

Another current type of ULP receive frontend is an intermediate frequency (IF) frontend with a continuous-time mixer and amplifiers. This type of frontend exhibits good sensitivity and selectivity characteristics, but consumes a relatively large amount of power.

Current ULP receiver frontends tend to rely on continuous-time analog approaches to receive, process, translate, and transmit RF signals in sensor networks.

It would be desirable to have a ULP receiver that overcomes the stated challenges of the current solutions. It would be desirable to have a ULP receiver that operates at very low power, and exhibits: above-average sensitivity; random pulsed interferer rejections; yield over process; voltage and temperature (PVT) variations; and security against replay or energy attacks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a die including circuit components of a ULP receiver according to an embodiment.

FIG. 1A is an illustration of a sensor node, according to an embodiment.

FIG. 2 is a system block diagram of a sensor node, according to an embodiment.

FIG. 3 is a block diagram of a wakeup receiver (WRX) circuit, according to an embodiment.

FIG. 4A is a diagram of a parallel radio frequency (RF) rectification circuit, according to an embodiment.

FIG. 4B is a diagram of a charge-transfer summation amplification (CTSA) circuit, according to an embodiment.

FIG. 4C is a diagram of a successive approximation analog-to-digital (SAR ADC) circuit, according to an embodiment.

FIG. 5 is block diagram showing clock generation circuit inputs and outputs, according to an embodiment.

FIG. 6 is a series of signal timing diagrams illustrating ULP receiver operation, according to an embodiment.

DETAILED DESCRIPTION

Embodiments of the invention include a wakeup receiver (WRX) featuring a charge-domain analog front end (AFE) with parallel radio frequency (RF) rectifier, charge-transfer summation amplifier (CTSA), and successive approximation analog-to-digital converter (SAR ADC) stages. In a particular embodiment, the invention includes a 3.2 μW WRX with simplified 802.15.4g medium access control/physical layer (MAC/PHY) baseband, received signal strength indicator (RSSI) and clear channel assessment (CCA), forward error correction (FEC), and a cryptographic checksum for industrial IoT applications. The charge-domain AFE provides a conversion gain of 26 dB with no static bias currents used anywhere in the rectifier, CTSA, or SAR ADC. This provides robustness to process, voltage and temperature (PVT) variation, and pulsed interference rejection.

Embodiments combine an ADC, a FIR filter and digital baseband to make a wakeup radio. A FIR filter can be implemented by changing the CT value overtime as the filter coefficient and summing with previous ADC samples. ASK modulation and Manchester encoding is supported. On-off keying (OOK) is a subset of ASK modulation. With the ADC, the WRX is able to support additional information encoded in the ASK RF message. Manchester is also supported. Multiple carrier frequencies are supported. Aa an example, 100 MHz to 3 GHz is used for a practical performance. However, embodiments are capable of frequencies as low as ˜10 MHz and as high as 100 GHz depending on the quality factor of matching network 302.

FIG. 1 is an illustration of a die layout (also referred to here as integrated circuit (IC)) 101 including circuit components of a ULP receiver according to an embodiment. The die includes an integrated CTSA and ADC 104, a clock generation circuit (CLKGEN) 106, and an RF rectifier circuit 108. As will be described in further detail below, embodiments of the invention provide improvements by colocating capacitors of the CTSA with those of the ADC in the circuit 104.

FIG. 1A is an illustration of a sensor node 110, according to an embodiment. The sensor node 110 has a form factor of approximately 5×5×8 cm³. In this illustration, an antenna 112 is shown before the node unit is sealed. The IC 101 is present on the sensor node 110.

FIG. 2 is a system block diagram of a ULP receiver system. The system includes a Communication transceiver (Comm TRX) 202], a radio frequency switch (RF SW) 204, the antenna 112, energy harvesting input sources (EH-Sources) 208, and on-board sensors. A system-on-a-chip (SOC) 212 includes a microprocessor (MCU) 204, energy harvesting power management unit (EH-PMU) 206, CLK (or CLKGEN) 106, and WRX (also referred to herein as wakeup receiver or ULP receiver) 300.

FIG. 3 is a block diagram of WRX circuit 300, according to an embodiment. In an embodiment, the WRX 300 is a fully-integrated sub-GHz WRX with charge-domain analog front-end in 65 nm CMOS. WRX 300 incorporates a simplified 802.15.4g MAC/PHY baseband, RSSI and clear channel assessment, forward error correction, and a cryptographic checksum. It achieves a sensitivity of −67.5 dBm, SIR of −15.3 dB, RSSI accuracy of ±3 dB, and power of 3.2 μW across PVT variation.

The WRX 300 is fully integrated into a system-on-a-chip (SoC) designed for an energy-harvesting industrial IoT leaf node, but is suitable for any type of node. A leaf node is typically an outer node in a sensor network. Signals from antenna 112 go through matching network 302. A main RF path (Main) from the antenna 112 and a dummy path (Dummy) from a broadband load form a pseudo-differential signal that improves common-mode rejection. In an embodiment, a conventional FR-4 substrate (a known glass-reinforced epoxy laminate material for printed circuit boards) and on-board inductor and capacitor (LC) components are used for the matching network 302 to the custom antenna 112.

The charge-domain AFE 310 comprises parallel RF rectifiers 108, a charge-transfer summation amplifier (CTSA) 104A, and a 10-bit SAR ADC 104B. The AFE 310 processes signals in the discrete-time charge domain as opposed to the traditional continuous-time analog approach. No static bias currents are required, providing low-power and robust operation over a wide range of conditions. In an embodiment, the WRX 300 down converts a Manchester encoded on-off keying modulation (OOK) RF wakeup message to baseband and digitizes the signal for demodulation, while providing reliable and rapid in-band and out-of-band interference rejection. The WRX 300 supports received signal strength indicator (RSSI) and CCA, used by the network layer for continuous traffic monitoring and link quality measurement.

Baseband physical layer (BB PHY) 304 receives signals from the ADC 104B and outputs a fast wakeup signal 306 and a secure wakeup signal 308. The network can be configured for either fast wakeups of only a Sync Word or secure wakeups with a full WRX beacon packet with cryptographic checksum that includes a payload for data transfer without the need for a high-power receiver.

A CLKGEN circuit 106, as further described below, controls the operation of the WRX 300. WRX CLK signal originates from an on-chip clock source using an on-board crystal reference.

FIGS. 4A, 4B and 4C illustrate an embodiment of a charge domain AFE310 that features RF rectification, charge-transfer amplification, and SAR ADC conversion based on charge redistribution.

FIG. 4A is a diagram of an RF rectification circuit 108, according to an embodiment. In one embodiment, the RF rectification circuit 108 includes multiple Dickson rectifier chains in parallel and down converts the RF input signal to the rectifier cap C_R as static charge. A reset phase (controlled by reset signal rst) is used in every stage, making sure there is no intersymbol interference caused by residual charge on CR. This front-end therefore supports a wide dynamic range of input power levels (from sensitivity level up to 7 dBm) without automatic gain control.

In contrast to current solutions, parallel paths (leading to RECT_P_1 and RECT_P_2) achieve a high signal-to-noise ratio (SNR) and fast settling time. Specifically, longer chains (as in current solutions) produce higher settling times. As shown in FIG. 4A, embodiments include multiple (M) paths with (N) stages per path. e.g. 2×15, or 3×10. Then summing the M outputs from the N paths yields the final baseband output. This will settle faster than long chains because each M path is short (only N stages), yet has a better SNR compared to that of single N×M stages.

FIG. 4B is a diagram of a CTSA circuit 104B, according to an embodiment. The CTAA stage shares capacitors with ADC 104B, and performs differential discrete-time summation and amplification through switched-cap operation. CDAC_P and CDAC_N are reused by CTSA as C_O. The gain of the stage is determined by the capacitance ratio between C_T and the ADC 104B C_DAC. At the interface at the output of the M paths (from FIG. 4A) summation and gain occurs. This is done in the charge domain for more robust operation. The CTA circuit 104B effectively takes multiple input branches, and sums them to a single output, to provide both summation and gain. The CTSA circuit 104B takes in M analog inputs, and weights and sums each input on the output in the charge domain, understanding that the output cap of the charge domain amp is the sample cap of an ADC. First, two parallel rectifier chains down-convert the RF input signal onto C_rect as static charge. A reset phase in every stage prevents intersymbol interference caused by residual charge on C_rect and enables a wide dynamic range of input power levels without AGC. The following CTSA stage takes in parallel RF rectifier outputs, reuses ADC input DACs as its output capacitor C_O, and performs differential discrete-time summation and amplification by a gain of C_T/C_DAC. The differential ADC samples from the CTSA output at the end of every cycle and performs asynchronous SAR operation based on charge-scaling C_DAC.

No static bias is used in the circuit.

FIG. 4C is a diagram of a SAR ADC circuit 104B, according to an embodiment. Circuit 104B receives CTSA_N and CTSA_P from the previous stage 104A and performs A/D conversion to generate multiple bits of DOUT, which is for digital baseband demodulation.

FIG. 5 is block diagram showing a clock generator block (CLKGEN) 106 that supports the discrete-time charge domain operation. CLKGEN 106 takes in the WRX clock signal and outputs S₁, S₂ and reset (RST) signals using logic gates, flip flops, and delay lines. The charge-domain AFE 310 seamlessly integrates RF down-conversion, baseband amplification, and A/D conversion without requiring driving-buffers and level-shifting circuits at each interface, thus saving power. The charge-domain topology is inherently robust against PVT variation because it is first-order bias and V_th independent.

FIG. 6 shows the timing and signal diagram of the AFE 310. Three clocking phases are required in every cycle of charge-domain operation. During the reset phase, C_T is fully discharged, and C_DAC is charged to V_cm. During the pre-charge phase, inputs are reset to V_cm, and source nodes of all the NFETs are charged to V_cm-V_{th_n}, and V_cm+V_{th_p} for PFETs case. As a result, all the transistors serve as analog source followers in this phase. When in the amplify phase, the inputs connect to parallel rectifier outputs providing a delta V_in (w.r.t V_cm), and the switch controlled by S₂* is released, initiating charge redistribution between capacitors C_T and C_DAC. Therefore, the rectifier output is gained up by C_T/C_DAC due to charge conservation. The effective capacitance of C_T is tunable through a digitally controlled 6-bit capacitor bank, providing tunable gain in the AFE. Finally, the differential ADC samples from the CTA output at the end of every cycle and performs a 10-bit asynchronous SAR operation based on charge-scaling C_DAC.

In an embodiment, the WRX is fabricated in 65 nm CMOS and occupies 0.33 mm². It shows the measured results from 15 parts at 6 temperature points between −40° C. to 85° C. without any trimming. All measurements are reported with the SoC on-chip switching regulators and clock. Across PVT, the WRX achieves a mean sensitivity of −70.2 dBm for fast wakeup and −67.5 dBm for secure wakeup under 10% of packet error rate (PER), enabling in-network range in deployed industrial environments of 250 m, non-line-of-sight. It also demonstrates the in-band selectivity performance of the WRX under CW interference at −500 kHz offset. A mean signal-to-interference ratio (SIR) of −16.5 dB is measured for fast wakeup and −15.3 dB for secure wakeups. A −65 dB out-of-band SIR at 1.485 GHz offset (2.4 GHz) is achieved with the additional help from an on-board LC matching network without a SAW filter. In-band selectivity under AM-type interference of an OOK packet with the same bit rate is also measured, showing an SIR of 0 dB at 0 Hz offset, demonstrating a fast interference rejection capability. The WRX achieves an RSSI accuracy within ±3 dB from −67 dBm to −43 dBm without calibration. The measured power for secure wakeup is shown in FIG. 5, with a mean across PVT of 3.2 μW. A false-alarm rate of less than 10⁻³ is measured for both wakeup modes.

Claims

1. A circuit for radio frequency (RF) signal to baseband conversion, comprising: an RF rectifier circuit configured to receive an RF signal, wherein the RF rectifier processes the received RF signal as multiple signal paths M and with multiple stages N per path;an amplifier circuit configured to receive output from the RF rectifier circuit and perform summation and amplification operations on the received output from the multiple signal paths M;an analog-to-digital (ADC) circuit configured to receive an output of the amplifier circuit, and to convert the received output to a digital baseband format; anda baseband physical layer configured to receive signals from the ADC and to output a fast wakeup signal and a secure wakeup signal, wherein a wireless network in which the circuit resides is configurable for either fast wakeup signals of only a Sync Word or secure wakeup signals with a full wakeup receiver beacon packet with cryptographic checksum that includes a payload for data transfer without the need for a high-power receiver.

2. The circuit of claim 1, wherein the amplifier circuit is a charge domain amplifier circuit and at least the summation operation is performed in the charge domain.

3. The circuit of claim 1, wherein the received RF signal comprises amplitude shift keying (ASK) modulation.

4. The circuit of claim 1, wherein the received RF signal comprises Manchester encoding.

5. The circuit of claim 1, wherein the circuit is configured to operate at multiple carrier frequencies.

6. The circuit of claim 1, wherein the output of the circuit includes information regarding received signal strength.

7. The circuit of claim 1, wherein the ADC circuit is a successive approximation analog-to-digital (SAR ADC) circuit.

8. The circuit of claim 1, wherein the circuit does not include any static bias circuitry.

9. The circuit of claim 1, wherein the amplifier circuit is further configured to receive output from the RF rectifier circuit and perform a differencing operation on the received output.

10. A charge domain amplifier comprising: circuitry for receiving multiple input branches;circuitry for summing the multiple input branches to a single Output; andcircuitry for providing both summation and amplification in the time domain, wherein digital information is stored as sampled charge on capacitors obtained from a radio frequency (RF) source, and wherein an output of the amplifier comprises a sample capacitor of an analog-to-digital converter (ADC).

11. The amplifier of claim 10, further comprising circuitry for weighting and summing each input to be reflected on the single Output in the time domain.

12. The amplifier of claim 10, wherein the amplifier does not include any static bias circuitry.

13. A method for receiving and processing radio frequency (RF) signals, the method comprising: deploying a circuit for radio frequency (RF) signal to baseband conversion, wherein the circuit comprises, an RF rectifier circuit configured to receive an RF signal; andan amplifier circuit configured to receive output from the RF rectifier circuit, wherein the method comprises;the circuit processing the received RF signal as multiple, parallel input signal paths using the RF rectification circuit;the circuit performing summation and amplification operations on the output of the RF rectification circuit in the time domain using the amplifier circuit;the circuit generating a signal to an analog-to-digital converter (ADC circuits) from the amplifier circuit, wherein the ADC converts the received signal from the amplifier circuit to a digital baseband format; anda baseband physical layer configured to receive signals from the ADC and to output a fast wakeup signal and a secure wakeup signal, wherein a wireless network in which the circuit resides is configurable for either fast wakeup signals of only a Sync Word or secure wakeup signals with a full wakeup receiver beacon packet with cryptographic checksum that includes a payload for data transfer without the need for a high-power receiver.

14. The method of claim 13, wherein the amplifier circuit is a charge domain amplifier circuit and at least the summation operation is performed in the charge domain.

15. The method of claim 13, wherein the received RF signal comprises amplitude shift keying (ASK) modulation.

16. The method of claim 13, wherein the received RF signal comprises Manchester encoding.

17. The method of claim 13, wherein the circuit is configured to operate multiple carrier frequencies.

18. The method of claim 13, wherein the output of the circuit includes information regarding received signal strength.

19. The method of claim 13 wherein the ADC circuit is a successive approximation analog-to-digital (SAR ADC) circuit.

20. The method of claim 13, wherein the circuit does not include any static bias circuitry.

21. The method of claim 13, wherein the amplifier circuit is further configured to receive output from the RF rectifier circuit and perform a differencing operation on the received output.