Patent Application
20080039040
The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the accompanying drawings, in which like reference numerals refer to like parts.
In the illustrated embodiment, wireless communication device 10 comprises an antenna system 12 linked to a first radio or radio frequency (“RF”) module 14 for receiving and transmitting signals over wireless network such as an IEEE 802.11 (“WiFi”) network and a second radio or RF module 15 for receiving and transmitting signals over a cellular data network. These modules may be combined in a single module with appropriate switching circuitry in alternative embodiments. In the wireless communication device 10, signals are transmitted and received over the air by the antenna system 12 under the management of the radio module or modules 14, 15. The antenna system 12 may comprise a single antenna with sections for receiving the different frequency signals from the different networks covered, or may comprise separate WiFi and cellular antennae.
The first or WiFi radio module 14 is connected to a baseband interface 16, and interface 16 is connected to WiFi microprocessor 18. The second or cellular radio module 15 is connected to a cellular microprocessor 20 via baseband interface 22. The baseband interfaces 16 and 22 may be combined in a single unit. Cellular microprocessor 20 may be a CDMA microprocessor when the mobile device uses CDMA technology. Each baseband interface converts baseband signals received from the associated radio module to digital signals sent to the associated microprocessor, and converts digital signals from the associated processor into baseband signals to send to the radio module for transmission from the antenna to an associated base station in the cellular network or an associated access point in the WiFi network.
The CDMA microprocessor is connected to a speaker 24 and a microphone 25 via input/output (I/O) interfaces (not shown). Both microprocessors are connected to a display screen 26 of the wireless device via an I/O interface for display of received data and various other information, such as received signal strength or RSSI, which is typically displayed by means of an RSSI icon 28. The WiFi microprocessor may also be connected to the microphone and speaker where the device is configured to receive and transmit voice calls over a wireless data network e.g., voice over internet protocol (“VoIP”) technology.
The hardware, software, function and operation of a dual mode wireless communication device is known in the field and will therefore not be described in any more detail. Instead, the following description is concerned with the modification of such a device to implement the received signal strength notification system and method according to the exemplary embodiment of this invention, as illustrated in
In the exemplary embodiment the CDMA microprocessor and WiFi microprocessor carry out the steps indicated in
Range 1 from MAX to S1
Range 2 from S1 to S2
Range 3 from S2 to S3
. . .
Range n from S(n−1) to zero.
where S is the signal strength in dB. The configuration range data is stored in the data storage area of the WiFi microprocessor and used to monitor the WiFi signal strength received by the WiFi microprocessor.
If the sizes of the successive signal strength ranges are selected to be unequal, the configuration message 30 sent by the CDMA microprocessor will indicate that the type of configuration is unequal, and will also indicate the number of different ranges (e.g., n), and will list the start and end signal strength for each signal strength range to be monitored, i.e. MAX to S1, S1 to S2, S2 to S3 . . . and S(n−1) to 0. At step 32, the configuration data is stored by the WiFi microprocessor and used to monitor the received WiFi signal strength.
When the phone or other wireless device is in the CDMA or cellular mode, it will receive signals from the local CDMA base station and the CDMA microprocessor will control the RSSI icon 28 to display the current CDMA or cellular signal strength. When the phone is using WiFi, it displays the signal strength of the signal received from the associated access point of the WiFi network.
At step 34, when the WiFi microprocessor detects a change in the received signal strength of the WiFi signal, it will determine whether or not the RSSI has moved into a different signal strength range or level in accordance with the RSSI configuration message 30. At step 35, if the RSSI has moved into a different range, the WiFi microprocessor will prepare a notification message containing the current RSSI range or level. This message is then transmitted to the CDMA microprocessor via RSSI notification message 36, and the CDMA microprocessor will update the RSSI icon 28 to indicated the current WiFi signal strength at step 38.
The WiFi microprocessor continues to monitor the received WiFi signal strength at predetermined intervals while the device is operating in the WiFi mode, and when another change in signal strength is detected at step 40, it will again determine whether the new signal strength is in a different range from the previous signal strength. If the signal strength is in a new range, another notification message will be prepared with the current range/level of the WiFi signal at step 42. This message is transmitted to the CDMA microprocessor at step 44, which will again update the RSSI icon at step 45. The process will continue as indicated in
This system significantly reduces the number of messages back and forth between a cellular signal microprocessor and a WiFi microprocessor in a dual mode wireless communication device. As discussed above, existing solution require the CDMA microprocessor to query the WiFi microprocessor at periodic intervals, and the WiFi microprocessor to send the current WiFi signal strength each time a query is received, regardless of whether there has been any change in signal strength. In contrast, the system and method described in conjunction with
This system and method described in conjunction with
Those of skill in the art will appreciate that the various illustrative logical blocks, modules, and method steps described in connection with the above described figures and the embodiments disclosed herein can often be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention. In addition, the grouping of functions within a module, block, circuit or step is for ease of description. Specific functions or steps can be moved from one module, block or circuit to another without departing from the invention.
Moreover, the various illustrative logical blocks, modules, and methods described in connection with the embodiments disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, or microcontroller. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
Additionally, the steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, or any other form of storage medium. An exemplary storage medium can be coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can also reside in an ASIC.
The above description of the disclosed embodiment is provided to enable any person skilled in the art to make or use the invention. Various modifications to the exemplary embodiment described above and illustrated in the accompanying drawings will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the invention. Thus, it is to be understood that the description and drawings presented herein represent an exemplary embodiment of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.
