Patent Application
20250095714
A memory is a common semiconductor structure. As the size of the semiconductor structure continues to decrease, more memories may be incorporated into a chip to increase product capacity. In a dynamic random access memory (DRAM), data are required to be written into/read from memory cells by using word lines and bit lines based on a voltage applied to the word lines.
As the capacity of the DRAM increases, more memory cells are connected to a word line, and the distance between the word lines decreases, which may delay the speed. To improve the delay of word line voltage, a word line may be divided into a plurality of sub word lines and each sub word line may be driven by a sub word-line driver (SWD), where the SWD may be disposed in a word line drive circuit.
The present disclosure relates to the field of semiconductor technologies, and in particular, to a word line driver and a memory apparatus, which are at least advantageous in reducing turn-off current in a keeping transistor without increasing a layout area.
According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a word line driver, including: a first sub word-line driver, including a first keeping transistor, where the first keeping transistor is configured to provide a first preset voltage to a first word line in response to a driving signal; and a second sub word-line driver, including a second keeping transistor, where the second keeping transistor is configured to provide the first preset voltage to a second word line in response to the driving signal; where the first keeping transistor and the second keeping transistor each include: an active area, where the active area includes a main portion extending in a first direction and a protruding portion adjacent to a part of the main portion and located on one side of the main portion, and the protruding portion has a first source area and a second source area; a gate, where the gate is located at least above a partial area, opposite to the protruding portion, of the main portion; and a first drain area and a second drain area separately located in the main portion on two opposite sides of the gate in the first direction; where the first drain area, the gate, and the first source area constitute the first keeping transistor, while the second drain area, the gate, and the second source area constitute the second keeping transistor.
In some embodiments, the first source area and the second source area are the same source area.
In some embodiments, the active area further includes: a first recessed portion, where the first recessed portion is located in the main portion and recessed from a side wall, away from the protruding portion, of the main portion to the protruding portion; and the gate is further located above the first recessed portion.
In some embodiments, a bottom surface, facing the protruding portion, of the first recessed portion is located below the gate.
In some embodiments, the gate covers the entire first recessed portion, and also covers a partial area of the main portion adjacent to the first recessed portion in the first direction.
In some embodiments, the first recessed portion has two opposite end surfaces in the first direction; and in the first direction, the length of the main portion that is adjacent to one of the end surfaces and covered by the gate is a first length, the length of the main portion that is adjacent to the other end surface and covered by the gate is a second length, and the first length is equal to the second length.
In some embodiments, the gate includes a first portion and a second portion that constitute a T shape, the first portion is close to the protruding portion relative to the second portion, and the first portion serves as a transverse edge of the T shape; and the first recessed portion is located within an orthographic projection of the second portion in the active area.
In some embodiments, an orthographic projection of the gate on the active area is rectangular or H-shaped.
In some embodiments, the active area further includes: a second recessed portion, where the second recessed portion is located within the main portion and recessed away from the protruding portion from the main portion to a side wall of the protruding portion, the second recessed portion is located between the source area and the drain area, and the second recessed portion is staggered with the protruding portion in the first direction; the gate is further located above a part of the second recessed portion; and a third recessed portion, where the third recessed portion is located within the main portion and recessed away from the protruding portion from the main portion to the side wall of the protruding portion, the third recessed portion is located between the second source area and the second drain area, and the third recessed portion is staggered with the protruding portion in the first direction; and the gate is further located above a part of the third recessed portion.
In some embodiments, the protruding portion includes: a first protruding portion and a second protruding portion located on two opposite sides of the main portion separately, where the first protruding portion has the first source area, and the second protruding portion has the second source area.
In some embodiments, the first keeping transistor and the second keeping transistor constitute a keeping transistor cell; and the word line driver includes a plurality of keeping transistor cells; where two of the keeping transistor cells mirror symmetrically in a second direction, the second direction is perpendicular to the first direction, and the active areas corresponding to the two opposite keeping transistor cells in the second direction share the same protruding portion and the same source area.
In some embodiments, the first sub word-line driver further includes: a first pull-up transistor, configured to pull up the first word line to a second preset voltage in response to a first enable signal provided by a first main word line, where the second preset voltage is greater than the first preset voltage; and a first pull-down transistor, configured to pull down the first word line to the first preset voltage in response to the first enable signal provided by the first main word line; where the first pull-down transistor is disposed on a side, away from the second keeping transistor, of the first keeping transistor, and the first pull-down transistor is disposed adjacent to the first keeping transistor; the second sub word-line driver further includes: a second pull-up transistor, configured to pull up the second word line to the second preset voltage in response to a second enable signal provided by a second main word line, where the second preset voltage is greater than the first preset voltage; and a second pull-down transistor, configured to pull down the second word line to the first preset voltage in response to the second enable signal provided by the second main word line, where the second pull-down transistor is disposed on a side, away from the first keeping transistor, of the second keeping transistor, and the second pull-down transistor is disposed adjacent to the second keeping transistor.
In some embodiments, the first pull-down transistor and the first keeping transistor share the first drain area; and the second pull-down transistor and the second keeping transistor share the second drain area.
In some embodiments, both the first keeping transistor and the second keeping transistor are NMOS transistors.
According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure provides a memory apparatus, including: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, where the memory cells are connected to the corresponding word lines and the corresponding bit lines; and the word line driver provided by any of the foregoing embodiments.
Technical solutions provided in the embodiments of the present disclosure have at least the following advantages:
The word line driver provided in the embodiments of the present disclosure includes a first sub word-line driver with a first keeping transistor and a second sub word-line driver with a second keeping transistor, where a length direction of a channel area between the first source area and first drain area of the first keeping transistor tilts relative to an extension direction of the active area, which can increase the length of the channel area of the first keeping transistor without increasing the layout area, thereby reducing turn-off current in the first keeping transistor and then ensuring that the first word line can be completely turned off, that is, the first word line can be thoroughly pulled down to the first preset voltage by using the first keeping transistor. Similarly, a length direction of a channel area between the second source area and second drain area of the second keeping transistor tilts relative to the extension direction of the active area, which can increase the length of the channel area of the second keeping transistor without increasing the layout area, thereby reducing turn-off current in the second keeping transistor and then ensuring that the second word line can be completely turned off, that is, the second word line can be thoroughly pulled down to the first preset voltage by using the second keeping transistor.
One or more embodiments are illustrated through corresponding drawings, and these illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings are not limited proportionally. In order to describe the technical solutions in the embodiments of the present disclosure or in the conventional technologies more clearly, the drawings to be used in the embodiments will be introduced simply. Apparently, the drawings described below are merely some embodiments of the present disclosure. Those of ordinary skill in the art may obtain other drawings according to these drawings without any creative efforts.
A word line driver includes a plurality of sub word-line drivers, and each of the sub word-line drivers includes a pull-down transistor and a keeping transistor.
A channel length of the keeping transistor is determined by a length of the corresponding gate in an extension direction of the active area. To reduce turn-off current in the keeping transistor, the channel length may be increased and the length of the corresponding gate in the extension direction of the active area 101 may be increased. However, the area occupied by the gate in the layout also increases accordingly. As a result, an area in the layout where the conductive plug 15 may be designed will be reduced, and requirements for a lithography process for forming the conductive plug 15 are higher. In particular, the smaller area enclosed by the gate 12 will increase the process difficulty of forming the conductive plug 15 within the area enclosed by the second gate 12. In addition, this method will also be limited by process limits.
The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Those of ordinary skill in the art may understand that, in the embodiments of the present disclosure, many technical details are provided for readers to understand the present disclosure better. However, the technical solutions of the present disclosure may still be implemented even without these technical details and various changes and modifications in the following embodiments.
With reference to
In the foregoing embodiment, the first source area S1 of the first keeping transistor N23 is located on the protruding portion 121, the protruding portion 121 is located on an outer side of the main portion 111 extending in the first direction X, that is, the first drain area D1 and the first source area S1 are not arranged in the first direction X, and compared with a solution in which the first drain area and the first source area are located on two opposite sides of the gate in the first direction, a direction from the first source area S1 to the first drain area D1 tilts relative to the first direction X in the foregoing embodiment, so that the first keeping transistor N23 has a larger channel length, which is beneficial to reducing turn-off current in the first keeping transistor N23 and enables the first word line to be completely turned off. Similarly, a direction from the second source area S2 to the second drain area D2 also tilts relative to the first direction X in the foregoing embodiment, so that the second keeping transistor N27 also has a larger channel length, which is beneficial to reducing turn-off current in the second keeping transistor N27.
The word line driver provided in the embodiments of the present disclosure will be described in more details below with reference to the drawings.
The active area 101 is an AA area, commonly referred to as an Active Area. The first source area S1 and the first drain area D1 are used for defining a source and a drain of the first keeping transistor N23 separately; and the second source area S2 and the second drain area D2 are used for defining a source and a drain of the second keeping transistor N27 separately.
The first keeping transistor N23 has an effect of ensuring that voltage in the first word line WL3 is pulled down to the first preset voltage VL after the first word line WL3 changes from a selected state (namely, activated state) to an unselected state (namely, closed state), thereby avoiding a problem that the first word line WL3 cannot be completely closed due to interference such as noise. The second keeping transistor N27 has an effect of ensuring that voltage in the second word line WL7 is pulled down to the first preset voltage VL after the second word line WL7 changes from a selected state to an unselected state, thereby avoiding a problem that the second word line WL7 cannot be completely closed due to interference such as noise.
Both the first source area S1 and the second source area S2 are connected to a preset power supply, and a level of the preset power supply is the first preset voltage, or a level of the preset power supply is equivalent to the first preset voltage VL. It may be understood that “equivalent” refers to a difference between the level of the preset power supply and the first preset voltage VL within an allowable range, and the levels of the two may be considered as the same within this allowable range. That is, in a circuit corresponding to the word line driver, the first source area S1 and the second source area S2 may be considered as nodes having the same potential, namely, the first source area S1 and the second source area S2 are electrically connected.
In some embodiments, with reference to
In other embodiments, with reference to
Moreover, in some embodiments, the gate 102 may further be located above the first recessed portion 131, which is beneficial to increasing the volume of the gate 102 and reducing the resistance of the gate 102.
The first recessed portion 131 may be recessed in a square or arc shape. In some embodiments, in a direction perpendicular to the first direction X1, a maximum depression depth of the first recessed portion 131 is defined as a first width W1, and a maximum width of the main portion 111 is defined as a second width W2. To ensure that the first recessed portion 131 has enough ability to suppress the electric leakage between the first drain area D1 and the second drain area D2, the first keeping transistor N23 and the second keeping transistor N27 have relatively high saturation current Idast, and the first keeping transistor N23 and the second keeping transistor N27 have relatively low turn-off current Ioff. A ratio of the first width W1 to the second width W2 is within a range of 0.3-0.7. In a specific example, the ratio of the first width W1 to the second width W2 is within a range of 0.4-0.6, such as 0.45, 0.5, or 0.55, which is beneficial to further ensuring the relatively low turn-off current Ioff on the premise of the relatively high saturation current.
In some embodiments, the gate 102 may cover the entire first recessed portion 131, and also cover a partial area of the main portion 111 adjacent to the first recessed portion 131 in the first direction X. That is, the first recessed portion 131 completely falls into an area covered by the gate 102. On the one hand, the area covered by the gate 102 is relatively large, so that the gate 102 has a relatively large volume, which is beneficial to reducing the resistance of the gate 102. On the other hand, the gate 102 covers the entire first recessed portion 131. On the premise of this position relationship, the gate 102 further covers a part of the main portion 111 adjacent to the first recessed portion 131, so that both the first keeping transistor N23 and the second keeping transistor N27 have relatively large sizes, that is, the first keeping transistor and the second keeping transistor occupy a relatively large active area, which improves the saturation current. Moreover, the gate 102 covers the entire first recessed portion 131, so that the process for forming the gate 102 has a relatively large process window, which reduces difficulties of the process for forming the gate 102.
In some embodiments, the first recessed portion 131 may be full of the isolation structure. In other embodiments, the gate 102 may cover a bottom surface and side walls of the first recessed portion 131. In this case, the bottom surface and side walls, covered by the gate 102, of the first recessed portion 131 also serve as a part of a channel. This can increase the area of the channel controlled by the gate 102 to improve the ability of the gate 102 to control channel conduction. Moreover, because a gate conductive layer in the gate 102 is correspondingly located within the first recessed portion 131, which can increase the volume of the gate 102 and further reduce the resistance of the gate 120. It may be understood that the channel includes the first channel corresponding to the first keeping transistor N23 and the second channel corresponding to the second keeping transistor N27. The gate 102 includes a gate dielectric layer and a gate electrode layer located on a surface of the gate dielectric layer. The gate 102 covers a bottom surface and side walls of the first recessed portion 131, indicating that the gate dielectric layer is located on the bottom surface and side walls of the first recessed portion 131 and the gate conductive layer is further located within the first recessed portion 131.
In a specific example, the gate 102 may cover a part of the bottom surface and a part of the side walls, and correspondingly, an isolation structure may be filled below the gate 102 in the first recessed portion 131. In another specific example, the gate 102 may cover all the bottom surface and all the top surface,
In other embodiments, the gate 102 may alternatively cover only a partial area of the first recessed portion 131, for example, a partial area, facing the protruding portion 121, of the first recessed portion 131 is covered by the gate 102, while the remained area, away from the protruding portion 121, of the first recessed portion 131 is not covered by the gate 102. Alternatively, the gate 102 and the first recessed portion 131 may be completely staggered.
In some embodiments, the bottom surface, facing the protruding portion 121, of the first recessed portion 131 may be located below the gate 102. In other embodiments, the bottom surface, facing the protruding portion 121, of the first recessed portion 131 may alternatively be flush with a side surface, away from the protruding portion 121, of the gate 102.
In addition, the first recessed portion 131 may have two opposite end surfaces in the first direction X; and in the first direction X, the length of the main portion 111 that is adjacent to one of the end surfaces and covered by the gate 102 is a first length L1, the length of the main portion 111 that is adjacent to the other end surface and covered by the gate 102 is a second length L2, and the first length L1 may be equal to the second length L2. That is, in the first direction X, the first recessed portion 131 is located in the middle of the gate 102, which is beneficial to improving symmetry of the first keeping transistor N23 and the second keeping transistor N27 and reducing the mismatch of different transistors.
It may be understood that, in other embodiments, the first length L1 may alternatively be different from the second length L2, for example, the first length L1 may be less than or greater than the second length L1.
In some embodiments, with reference to
The first recessed portion 131 may be located within an orthographic projection of the second portion 122 in the active area 101. In addition, the first recessed portion 131 may have two opposite end surfaces in the first direction; and in the first direction X, the length of the main portion 111 that is adjacent to one of the end surfaces and covered by the second portion 122 is a first length L1, the length of the main portion 111 that is adjacent to the other end surface and covered by the second portion 122 is a second length L2, and the first length L1 may be equal to the second length L2.
In other embodiments, an orthographic projection of the gate 102 on the active area 101 may be rectangular or H-shaped. In a specific example, the H-shaped gate 102 includes two opposite crossbeams and a connecting portion located between the crossbeams, where the two crossbeams are arranged in the first direction X, and the first recessed portion 131 may alternatively be located below the connecting portion.
The second recessed portion 141 is configured to further increase the length of the channel area in the first keeping transistor N23 and further reduce the turn-off current in the first keeping transistor N23.
With continued reference to
The third recessed portion 151 is configured to further increase the length of the channel area in the second keeping transistor N27 and further reduce the turn-off current in the second keeping transistor N27.
With continued reference to
Understandably, in a specific example, the active area 101 may include any one or more of the first recessed portion 131, the second recessed portion 141, or the third recessed portion 151.
Correspondingly, with reference to
With reference to
The working principle of the first sub word-line driver SWD1 as an example will be explained below.
The first enable signal includes a first state and a second state, and a level of the first state is different from that of the second state; when the first enable signal is in the first state, the first sub word-line driver SWD1 receives a valid driving signal, the first pull-up transistor P13 is turned on, the first sub line WL3 is pulled up to the second preset voltage PXID, and the second preset voltage PXID is the same as or equivalent to a voltage of the driving signal; and when the first enable signal is in the second state, the first pull-down transistor N13 is turned on, the first word line WL3 is pulled down to the first preset voltage VL, and the first keeping transistor N23 is turned on, thereby further ensuring that the first word line WL3 is pulled down to the first preset voltage VL and avoiding interference of signal noise to the first word line WL3.
The working principle of the second sub word-line driver may be referenced to the working principle of the first sub word-line driver, and will not be repeated here. In a specific example, both the first pull-up transistor P13 and the second pull-up transistor P17 may be PMOS transistors, and both the first pull-down transistor N13 and the second pull-down transistor N17 may be NMOS transistors. Both the first keeping transistor N23 and the second keeping transistor N27 may be NMOS transistors.
With reference to
It should be noted that, for the convenience of illustration and explanation, the channel areas of the transistors corresponding to the active area are marked by N13, N23, P13, N17, N27, and P17 in
The first pull-down transistor N13 and the first keeping transistor N23 may share the first drain area D1. By sharing the first drain area D1, a drain of the first pull-down transistor and the drain of the first keeping transistor are electrically connected without additional contact structures and metal layers, which reduces complexity of the layout structure. The second pull-down transistor N17 and the second keeping transistor N27 may share the second drain area D2. By sharing the second drain area D2, a drain of the second pull-down transistor and the drain of the second keeping transistor are electrically connected without additional contact structures and metal layers, which reduces complexity of the layout structure.
It should be noted that, for the convenience of illustration and explanation, in
In some embodiments, with reference to
In other embodiments, the two first keeping transistors in the two keeping transistor cells 10 may share the same source area located in the same protruding portion 121, and the two second keeping transistors do not share the source area with the first keeping transistors. Alternatively, the two second keeping transistors of the two keeping transistor cells 10 may share the same source area located in the same protruding portion 121, and the two first keeping transistors do not share the same source area with the second keeping transistors.
The word line driver may further include: a plurality of contact structures 105, where each of the contact structures 105 is used for electrical connection with the corresponding first source area S1, second source area S2, first drain area D1, or second drain area D2, and also for electrical connection with the source or drain area of the first pull-down transistor, second pull-down transistor, first pull-up transistor, or second pull-up transistor.
According to the word line driver provided in the foregoing embodiment, channel length directions of two keeping transistors are designed to tilt relative to the extension direction of the active area 101, which can increase channel lengths of the keeping transistors without increasing the layout area, thereby reducing turn-off current in the keeping transistors and improving the ability of the keeping transistors to turn off the word lines connected to the keeping transistors. Moreover, the channel length directions tilt relative to the extension direction of the active area 101, which can also reserve more space for laying the contact structures 105 and improve spatial utilization of the layout.
Correspondingly, an embodiment of the present disclosure further provides a memory apparatus, including the word line driver provided by the foregoing embodiments. The memory apparatus provided by the embodiment of the present disclosure will be explained in detail below. For the same or corresponding parts as the foregoing embodiments, reference may be made to the detailed explanation of the foregoing embodiments, and details will not be repeated below.
The memory apparatus provided by the embodiment of the present disclosure includes: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, where the memory cells are connected to the corresponding word lines and the corresponding bit lines; and the word line driver provided by the foregoing embodiments.
Each sub word-line driver in the word line driver is electrically connected to a corresponding word line to select/activate the corresponding word line or close the corresponding word line.
The memory apparatus may be a DRAM system, such as a DDR5 DRAM system or a DDR4 DRAM system. In other embodiments, the memory apparatus may alternatively be an SRAM system, an SDRAM system, an ROM system, or a flash memory system.
Those of ordinary skill in the art may understand that the foregoing implementations are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211138984.0 | Sep 2022 | CN | national |
This is a continuation of International Patent Application No. PCT/CN2022/129996 filed on Nov. 4, 2022, which claims priority to Chinese Patent Application No. 202211138984.0, filed on Sep. 19, 2022. The disclosure of these applications is hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2022/129996 | Nov 2022 | WO |
| Child | 18963713 | US |
