The present embodiments relate to processing of NAND devices and, more particularly, to approaches for direct wordline contact formation for 3D NAND devices.
In accordance with current substrate (e.g., wafer) manufacturing approaches, etch speed, etch profile, and etch selectivity are optimized to lower manufacturing cost and increase circuit element density on a substrate. Etch features, such as memory holes, continue to shrink in size and/or increase in aspect ratio (e.g., ratio of depth to width of a feature), however. For example, in three dimensional (3D) NAND device manufacturing, substrates can include up to 96 layers and can extend up to 128 layers. Additionally, an aspect ratio of a memory hole, for example, can be between 100 to 200 with a memory hole depth ranging from about 6 μm to 8 μm, thus making memory hole etching one of the most critical and challenging steps when manufacturing 3D NAND devices. For example, such high aspect ratio etching not only requires high etching speed and high etching selectivity, e.g., to mask material on a substrate, but it also requires a straight profile without bowing and twisting, no under-etch and minimum micro-loading, minimum aspect ratio dependent etching (ARDE), and uniformity across the entire substrate (e.g., critical dimension (CD) variation of 3σ<1%).
When manufacturing 3D NAND devices having a staircase arrangement of layers, wordline landing pad formation is defined first through staircase formation (e.g., lithography and etch steps) and/or a chop process in which multiple layers are etched down, followed by a staircase area gap fill. However, selectivity margin during wordline contact etching remains a challenge, as contact holes with different height are formed in a same etch step. Furthermore, using higher dry etch-process temperatures to increase selectivity is constrained by hardware limits.
It is with respect to these and other considerations that the present disclosure is provided.
In view of the foregoing, a method may include providing a first film stack comprising a first plurality of alternating first layers and second layers, and forming a first plurality of contact openings in the first film stack, wherein each contact opening of the first plurality of contact openings is formed to a different etch depth relative to an upper surface of the first film stack. The method may further include forming a sacrificial gapfill within the first plurality of contact openings, and forming a second film stack atop the upper surface of the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The method may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and removing the sacrificial gapfill from the first plurality of contact openings.
In some approaches, a system may include a processor, and a memory storing instructions executable by the processor to provide a first film stack comprising a first plurality of alternating first layers and second layers, and to form a first plurality of contact openings in the first film stack, wherein each contact opening of the first plurality of contact openings is formed to a different etch depth relative to an upper surface of the first film stack. The memory may further store instructions operable by the processor to form a sacrificial gapfill within the first plurality of contact openings, and to form a second film stack atop the upper surface of the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The memory may further store instructions operable by the processor to form a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and to remove the sacrificial gapfill from the first plurality of contact openings.
In some approaches, a memory device may include a stack of layers comprising a first film stack and a second film stack, wherein the stack of layers includes a plurality of alternating first layers and wordlines oriented horizontally, and a first plurality of contact openings and a second plurality of contact openings formed vertically through the first film stack and the second film stack, wherein each contact opening of the first and second plurality of contact openings extends to an upper surface of the stack of layers, and wherein each contact opening of the plurality of contact openings is formed to a different etch depth relative to the upper surface of the stack of layers. The memory device may further include a wordline contact formed within each contact opening of the plurality of contact openings.
The accompanying drawings illustrate exemplary approaches of the disclosure, including the practical application of the principles thereof, as follows:
The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict exemplary embodiments of the disclosure, and therefore are not be considered as limiting in scope. In the drawings, like numbering represents like elements.
Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines otherwise visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
Methods, systems, and devices in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where various embodiments are shown. The methods, systems, and devices may be embodied in many different forms and are not to be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so the disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.
Embodiments described herein are directed to 3D NAND wordline contact-first approaches with higher feasibility to integrate with other high-aspect ratio modules together (e.g., slit and CMOS contact). Direct wordline contact techniques of the present disclosure can reduce multiple conventional processing steps (e.g., staircase formation lithography and etching, chop lithography and etching, staircase area gapfill deposition and planarization), and thus provides significant throughput and cost benefits. Furthermore, by forming wordline contact openings before wordline metal deposition, contact metal selectivity is improved and the use of stop layers and wordline landing pads may be eliminated. Still furthermore, the approaches of the present disclosure allow a larger CD at a lower tier of the device, which can increase contact landing margin and relax the burden of lithography alignment error.
As further shown, the device 100 may include a first masking layer 110 formed directly atop an upper surface 112 of the first film stack 102. The first masking layer 110 may be a photoresist layer including a set (i.e., one or more) of first mask openings 115A, 115B formed (e.g., etched) therein. As shown, the first mask openings 115A, 115B may be formed selective to the upper surface 112 of the first film stack 102.
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The sacrificial gapfill 127 may then be removed, as shown in
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A plurality of wordlines 152 may then be formed in the device 100, as demonstrated in
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In some embodiments, the first deposition chamber 410A may be used to deposit the first film stack 102 as alternating first layers 106A-106E and second layers 108A-108D, and to deposit the second film stack 103 as alternating first layers 113A-113D and second layers 111A-111D. The first deposition chamber 410A may be further used to deposit the plurality of masking layers (e.g., the first masking layer 110, the second masking layer 124, and the third masking layer 132) over the first film stack 102.
The first etch chamber 410B may be used to etch the plurality of masking layers and to form the plurality of contact openings (e.g., the first contact opening 118A, the third contact opening 128A, the third contact opening 128B, and the fourth contact opening 136). The first etch chamber 410B may be further used to form the first plurality of contact openings in the first film stack 102 and the second plurality of contact openings in the second film stack 103. The first etch chamber 410B may be further used to punch through the liner 140 along the bottom 149 of each contact opening of the first and second plurality of contact openings.
The second deposition chamber 410C may be used to deposit the liner 140 over the device 100, including within each contact opening of the first and second plurality of contact openings, and to deposit the sacrificial gapfill 127 within the first plurality of contact openings.
The second etch chamber 410D may be used to remove the first layers 106A-106E and the first layers 113A-113D to form the plurality of wordline openings 150 in the first and second film stacks 102, 103. In some embodiments, a wet etch process may be performed in the second etch chamber 410D.
The third deposition chamber 410E may be used to form the plurality of wordlines 152 by depositing the first conductive material 154 within the plurality of wordline openings 150. The third deposition chamber 410E (or another deposition chamber) may be further used to deposit the second conductive material 160 within the first and second plurality of contact openings to form the plurality of wordline contacts 162 within the device 100.
A system controller 420 is in communication with the robot 404, the transfer station/chamber 402, and the plurality of processing chambers 410A-410E. The system controller 420 can be any suitable component that can control the processing chambers 410A-410E and robot(s) 404, as well as the processes occurring within the process chambers 410A-410E. For example, the system controller 420 can be a computer including a central processing unit 422, memory 424, suitable circuits/logic/instructions, and storage.
Processes or instructions may generally be stored in the memory 424 of the system controller 420 as a software routine that, when executed by the processor 422, causes the processing chambers 410A-410N to perform processes of the present disclosure. The software routine may also be stored and/or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor 422. Some or all of the method(s) of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor 422, transforms the general purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.
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At block 502, the process 500 may include forming a plurality of contact openings in the first film stack, wherein each contact opening of the plurality of contact openings is formed to a different etch depth relative to an upper surface of the film stack. In some embodiments, forming the plurality of contact openings in the film stack may include patterning a first set of openings through a first masking layer, and etching, through the first set of openings, a first set of contact openings of the plurality of contact openings. Forming the plurality of contact openings in the film stack may further include patterning a second set of openings through a second masking layer, wherein one opening of the second set of openings is aligned with one contact opening of the first set of contact openings, and etching, through the second set of openings, a second set of contact openings of the plurality of contact openings. Forming the plurality of contact openings in the film stack may further include patterning a third set of openings through a third masking layer, wherein the third masking layer is formed over the first and second sets of contact openings, and etching, through the third set of openings, a third set of contact openings of the plurality of contact openings. In some embodiments, a first depth of the first set of contact openings is less than a second depth of the second set of contact openings, which is less than a third depth of the third set of contact openings.
At block 503, the process 500 may include forming a sacrificial gapfill within the first plurality of contact openings. In some embodiments, the sacrificial gapfill may be deposited and then planarized.
At block 504, the process 500 may include forming a second film stack atop the upper surface of the first film stack, wherein the second film stack includes a second plurality of alternating first and layers and second layers.
At block 505, the process 500 may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill.
At block 506, the process 500 may further include removing the sacrificial gapfill from the first plurality of contact openings. In some embodiments, the sacrificial gapfill may be etched.
At block 507, the process 500 may include depositing a liner over the second film stack including within each contact opening of the first and second plurality of contact openings.
At block 508, the process 500 may include removing the first layers to form a plurality of wordline openings in the first and second film stacks. In some embodiments, the wordline openings are formed using a lateral wet etch process.
At block 509, the process 500 may include forming a plurality of wordlines by depositing a first conductive material within the plurality of wordline openings. In some embodiments, the first conductive material is W or Mo.
At block 510, the process 500 may include removing the liner from a bottom of each contact opening of the plurality of contact openings. In some embodiments, removing the liner from the bottom of each contact opening of the first and second plurality of contact openings exposes an upper surface of one or more of the plurality of wordlines. In some embodiments, the liner is removed from the bottom of each contact opening of the first and second plurality of contact openings without removing the liner from a sidewall of each contact opening of the first and second plurality of contact openings.
At block 511, the process 500 may include depositing a second conductive material within the first and second plurality of contact openings to form a plurality of wordline contacts. In some embodiments, the second conductive material may be W, which is deposited together with TiN, atop an upper surface of the plurality of wordlines.
In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers of the device, e.g., as described herein. For example, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance running software, or implemented in hardware.
For the sake of convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal” will be used herein to describe the relative placement and orientation of components and their constituent parts as appearing in the figures. The terminology will include the words specifically mentioned, derivatives thereof, and words of similar import.
As used herein, an element or operation recited in the singular and proceeded with the word “a” or “an” is to be understood as including plural elements or operations, until such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the present disclosure are not intended as limiting. Additional embodiments may also incorporate the recited features.
Furthermore, the terms “substantial” or “substantially,” as well as the terms “approximate” or “approximately,” can be used interchangeably in some embodiments, and can be described using any relative measures acceptable by one of ordinary skill in the art. For example, these terms can serve as a comparison to a reference parameter, to indicate a deviation capable of providing the intended function. Although non-limiting, the deviation from the reference parameter can be, for example, in an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.
Still furthermore, one of ordinary skill will understand when an element such as a layer, region, or substrate is referred to as being formed on, deposited on, or disposed “on,” “over” or “atop” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly over” or “directly atop” another element, no intervening elements are present.
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Furthermore, the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose. Those of ordinary skill in the art will recognize the usefulness is not limited thereto and the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below are to be construed in view of the full breadth and spirit of the present disclosure as described herein.
This application claims priority to U.S. provisional patent application Ser. No. 63/429,856, filed on Dec. 2, 2022, entitled “Wordline Contact Formation for NAND Device,” which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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63429856 | Dec 2022 | US |