Write amplification reduction by delaying read access to data written during garbage collection

Abstract

The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.

Description

TECHNICAL FIELD

The disclosed embodiments relate generally to memory systems, and in particular, to write amplification reduction, for example in flash memory devices.

BACKGROUND

Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. Non-volatile memory retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell.

Garbage collection is a process of memory management that reclaims portions of memory that no longer contain valid data. Using flash memory as an example, data is written to flash memory in units called pages, which are made up of multiple memory cells. However, flash memory is erased in larger units called blocks, which are made up of multiple pages. If some pages of a first block contain invalid data, those pages cannot be overwritten until the whole block containing those pages is erased. The process of garbage collection reads and re-writes the pages with valid data from the first block into a second block and then erases the first block. After garbage collection, the second block contains pages with valid data and free pages that are available for new data to be written. Since flash memory can only be programmed and erased a limited number of times, it is important to utilize a garbage collection scheme that maximizes or improves the life of a flash-based storage system.

SUMMARY

Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of various implementations are used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various implementations, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.

FIG. 1 is a block diagram illustrating an implementation of a data storage system, in accordance with some embodiments.

FIG. 2 is a block diagram illustrating an implementation of a management module, in accordance with some embodiments.

FIG. 3A is a prophetic diagram of voltage distributions that may be found in a single-level flash memory cell (SLC) over time, in accordance with some embodiments.

FIG. 3B is a prophetic diagram of voltage distributions that may be found in a multi-level flash memory cell (MLC) over time, in accordance with some embodiments.

FIG. 4A is a prophetic diagram of voltage distributions that may be found in a multi-level flash memory cell (MLC) after a coarse multi-bit programming operation, in accordance with some embodiments.

FIG. 4B is a prophetic diagram of voltage distributions that may be found in a multi-level flash memory cell (MLC) after a fine multi-bit programming operation, in accordance with some embodiments.

FIG. 5A is a prophetic diagram of voltage distributions that may be found in a multi-level flash memory cell (MLC) after a lower page programming operation, in accordance with some embodiments.

FIG. 5B is a prophetic diagram of voltage distributions that may be found in a multi-level flash memory cell (MLC) after an upper page programming operation, in accordance with some embodiments.

FIG. 6 illustrates a sequence of programming pages in a coarse/fine programming scheme, in accordance with some embodiments.

FIG. 7 illustrates a flowchart representation of a method of garbage collection in a storage system, in accordance with some embodiments.

FIG. 8 illustrates a flowchart representation of a method of writing data in a storage system, in accordance with some embodiments.

In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.

DETAILED DESCRIPTION

The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. Some implementations include systems, methods and/or devices to delay enabling read access to a write unit to which data was written during garbage collection until a predefined subsequent operation has been completed. Some implementations include systems, methods and/or devices to use lower page/upper page programming during write operations performed in response to a host command and to use coarse/fine programming during garbage collection.

More specifically, some implementations include a method of garbage collection in a storage system. In some implementations, the method includes during a garbage collection operation, while writing data to a sequence of write units of a storage medium block, delaying enabling read access to a respective write unit of the storage medium block, to which data was written during garbage collection, until a predefined subsequent operation on the storage medium block has been completed.

In some embodiments, the predefined subsequent operation on the storage medium block includes completion of writing data to at least N write units subsequent to writing data to the respective write unit.

In some embodiments, the predefined subsequent operation on the storage medium block includes completion of writing data to all remaining write units of the storage medium block subsequent to writing data to the respective write unit.

In some embodiments, the method further includes updating a translation table to point to the respective write unit after the predefined subsequent operation on the storage medium block has been completed.

In some embodiments, the sequence of write units is on a sequence of word lines.

In another aspect, a method of writing data in a storage system includes (1) during a garbage collection operation, while writing data to a first sequence of write units of a storage medium block, performing a coarse multi-bit write operation that partially programs each memory cell of a respective write unit with a plurality of bits, followed by a second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit with the plurality of bits, and (2) during a write operation, performed in response to a host command, while writing data to a second sequence of write units of the storage medium block, performing a lower page write operation that partially programs each memory cell of a respective write unit with a single, respective lower page bit, followed by an upper page write operation that completes programming of each memory cell of the respective write unit with a respective upper page bit.

In some embodiments, during the garbage collection operation, the method includes performing a second coarse multi-bit write operation that partially programs each memory cell of another write unit, distinct from the respective write unit, after the coarse programming of the respective write unit and prior to the second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit.

In some embodiments, the method further includes (1) when erasing data in the second sequence of write units, performing a default erase operation, and (2) when erasing data in the first sequence of write units, performing a shallow erase operation having a shorter duration than the default erase operation.

In some embodiments, the storage medium includes one or more non-volatile storage devices, such as flash memory devices.

In yet another aspect, any of the methods described above are performed by a device operable to perform garbage collection for a storage medium, the device including (1) a storage medium interface for coupling the device to the storage medium, and (2) one or more modules, including a memory management module that includes one or more processors and memory storing one or more programs configured for execution by the one or more processors, the one or more modules coupled to the storage medium interface and configured to perform any of the methods described above.

In yet another aspect, any of the methods described above are performed by a device operable to write data in a storage system, the device including (1) a storage medium interface for coupling the device to the storage medium, and (2) one or more modules, including a memory management module that includes one or more processors and memory storing one or more programs configured for execution by the one or more processors, the one or more modules coupled to the storage medium interface and configured to perform any of the methods described above.

In yet another aspect, a device is operable to perform garbage collection for a storage medium. In some embodiments, the device includes (1) a storage medium interface for coupling the device to the storage medium, and (2) means for, during a garbage collection operation, while writing data to a sequence of write units of a storage medium block, delaying enabling read access to a respective write unit of the storage medium block, to which data was written during garbage collection, until a predefined subsequent operation on the storage medium block has been completed.

In yet another aspect, a device is operable to write data in a storage system. In some embodiments, the device includes (1) a storage medium interface for coupling the device to the storage medium, (2) means for, during a garbage collection operation, while writing data to a first sequence of write units of a storage medium block, performing a coarse multi-bit write operation that partially programs each memory cell of a respective write unit with a plurality of bits, followed by a second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit with the plurality of bits, and (3) means for, during a write operation, performed in response to a host command, while writing data to a second sequence of write units of the storage medium block, performing a lower page write operation that partially programs each memory cell of a respective write unit with a single, respective lower page bit, followed by an upper page write operation that completes programming of each memory cell of the respective write unit with a respective upper page bit.

In yet another aspect, any of the methods described above are performed by a storage system comprising (1) a storage medium (e.g., comprising one or more non-volatile storage devices, such as flash memory devices) (2) one or more processors, and (3) memory storing one or more programs, which when executed by the one or more processors cause the storage system to perform or control performance of any of the methods described above.

In yet another aspect, a non-transitory computer readable storage medium stores one or more programs configured for execution by a device coupled to a storage medium, the one or more programs comprising instructions for causing the device and/or storage medium to perform any of the methods described above.

Numerous details are described herein in order to provide a thorough understanding of the example implementations illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.

FIG. 1 is a diagram of an implementation of a data storage system 100, in accordance with some embodiments. While some example features are illustrated, various other features have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the example implementations disclosed herein. To that end, as a non-limiting example, the data storage system 100 includes a memory controller 120, and a storage medium 130, and is used in conjunction with a computer system 110. In some implementations, storage medium 130 is a single flash memory device while in other implementations storage medium 130 includes a plurality of flash memory devices. In some implementations, storage medium 130 is NAND-type flash memory or NOR-type flash memory. Further, in some implementations memory controller 120 is a solid-state drive (SSD) controller. However, other types of storage media may be included in accordance with aspects of a wide variety of implementations.

Computer system 110 is coupled to memory controller 120 through data connections 101. However, in some implementations computer system 110 includes memory controller 120 as a component and/or a sub-system. Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device. Computer system 110 is sometimes called a host or host system. In some implementations, computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch screen display, a mouse, a track-pad, a digital camera and/or any number of supplemental devices to add functionality.

Storage medium 130 is coupled to memory controller 120 through connections 103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 130 and data values read from storage medium 130. In some implementations, however, memory controller 120 and storage medium 130 are included in the same device as components thereof. Furthermore, in some implementations memory controller 120 and storage medium 130 are embedded in a host device, such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed by the embedded memory controller. Storage medium 130 may include any number (i.e., one or more) of memory devices including, without limitation, non-volatile semiconductor memory devices, such as flash memory. For example, flash memory devices can be configured for enterprise storage suitable for applications such as cloud computing, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop and tablet computers.

Storage medium 130 is divided into a number of addressable and individually selectable blocks, such as selectable portion 131. In some implementations, the individually selectable blocks are the minimum size erasable units in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. Each block is usually further divided into a plurality of pages and/or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some implementations (e.g., using some types of flash memory), the smallest individually accessible unit of a data set, however, is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for reading data from the flash memory device.

For example, one block comprises any number of pages, for example, 64 pages, 128 pages, 256 pages or another suitable number of pages. Blocks are typically grouped into a plurality of zones. Each block zone can be independently managed to some extent, which increases the degree of parallelism for parallel operations and simplifies management of storage medium 130.

In some implementations, memory controller 120 includes a management module 121, a host interface 129, a storage medium interface (I/O) 128, and additional module(s) 125. Memory controller 120 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure more pertinent features of the example implementations disclosed herein, and a different arrangement of features may be possible. Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 130 though connections 103. In some implementations, storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 130 (e.g., reading threshold voltages for NAND-type flash memory).

In some implementations, management module 121 includes one or more processing units (CPUs, also sometimes called processors) 122 configured to execute instructions in one or more programs (e.g., in management module 121). In some implementations, the one or more CPUs 122 are shared by one or more components within, and in some cases, beyond the function of memory controller 120. Management module 121 is coupled to host interface 129, additional module(s) 125 and storage medium I/O 128 in order to coordinate the operation of these components.

Additional module(s) 125 are coupled to storage medium I/O 128, host interface 129, and management module 121. As an example, additional module(s) 125 may include an error control module to limit the number of uncorrectable errors inadvertently introduced into data during writes to memory or reads from memory. In some embodiments, additional module(s) 125 are executed in software by the one or more CPUs 122 of management module 121, and, in other embodiments, additional module(s) 125 are implemented in whole or in part using special purpose circuitry (e.g., to perform encoding and decoding functions).

During a write operation, host interface 129 receives data to be stored in storage medium 130 from computer system 110. The data held in host interface 129 is made available to an encoder (e.g., in additional module(s) 125), which encodes the data to produce one or more codewords. The one or more codewords are made available to storage medium I/O 128, which transfers the one or more codewords to storage medium 130 in a manner dependent on the type of storage medium being utilized.

A read operation is initiated when computer system (host) 110 sends one or more host read commands on control line 111 to memory controller 120 requesting data from storage medium 130. Memory controller 120 sends one or more read access commands to storage medium 130, via storage medium I/O 128, to obtain raw read data in accordance with memory locations (addresses) specified by the one or more host read commands. Storage medium I/O 128 provides the raw read data (e.g., comprising one or more codewords) to a decoder (e.g., in additional module(s) 125). If the decoding is successful, the decoded data is provided to host interface 129, where the decoded data is made available to computer system 110. In some implementations, if the decoding is not successful, memory controller 120 may resort to a number of remedial actions or provide an indication of an irresolvable error condition.

Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages. Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on). The magnitude of the charge, and the corresponding threshold voltage the charge creates, is used to represent one or more data values. In some implementations, during a read operation, a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.

The terms “cell voltage” and “memory cell voltage,” in the context of flash memory cells, means the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current. Similarly, reading threshold voltages (sometimes also called reading signals and reading voltages) applied to a flash memory cells are gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage. In some implementations, when a flash memory cell's transistor conducts current at a given reading threshold voltage, indicating that the cell voltage is less than the reading threshold voltage, the raw data value for that read operation is a “1,” and otherwise the raw data value is a “0.”

As explained above, a storage medium (e.g., storage medium 130) is divided into a number of addressable and individually selectable blocks and each block is optionally (but typically) further divided into a plurality of pages and/or word lines and/or sectors. While erasure of a storage medium is performed on a block basis, in many embodiments, reading and programming of the storage medium is performed on a smaller subunit of a block (e.g., on a page basis, word line basis, or sector basis). In some embodiments, the smaller subunit of a block consists of multiple memory cells (e.g., single-level cells or multi-level cells, as described below). In some embodiments, programming is performed on an entire page.

As an example, if data is written to a storage medium in pages, but the storage medium is erased in blocks, pages in the storage medium may contain invalid (e.g., stale) data, but those pages cannot be overwritten until the whole block containing those pages is erased. In order to write to the pages with invalid data, the pages with valid data in that block are read and re-written to a new block and the old block is erased (or put on a queue for erasing). This process is called garbage collection. After garbage collection, the new block contains pages with valid data and free pages that are available for new data to be written, and the old block that was erased is also available for new data to be written. Since flash memory can only be programmed and erased a limited number of times, the efficiency of the algorithm used to pick the next block(s) to re-write and erase has a significant impact on the lifetime and reliability of flash-based storage systems.

Write amplification is a phenomenon where the actual amount of physical data written to a storage medium (e.g., storage medium 130) is a multiple of the logical amount of data intended to be written by a host (e.g., computer system 110, sometimes called a host). As discussed above, when a storage medium must be erased before it can be re-written, the garbage collection process to perform these operations results in re-writing data one or more times. This multiplying effect increases the number of writes required over the life of a storage medium, which shortens the time it can reliably operate. The formula to calculate the write amplification of a storage system is given by equation (1):

$\begin{array}{cc}\frac{\mathrm{amount}\mathrm{of}\mathrm{data}\mathrm{written}\mathrm{to}a\mathrm{storage}\mathrm{medium}}{\mathrm{amount}\mathrm{of}\mathrm{data}\mathrm{written}\mathrm{by}a\mathrm{host}}& \left(1\right)\end{array}$

With the scaling of process nodes to sub-nanometer levels, endurance of storage mediums (e.g., NAND flash memories) is declining. Endurance degradation may result from drifting of cell voltages due to program disturb (e.g., during write operations), over programming, read disturb (e.g., during read operations), and retention effects. In order to maintain the reliability of the storage medium and avoid data loss, storage systems typically utilize background activities such as read disturb counters and/or read patrol mechanisms that check for counts of read and/or error thresholds to re-locate data before it is ECC uncorrectable. Read disturb is becoming increasingly difficult to manage, especially toward the end of life of a storage medium as data needs to be refreshed too often to maintain its reliability.

Further, operating at higher temperatures may cause retention charge loss on blocks that are cold (e.g., idle for an extended period of time from the last program command). Read patrolling is utilized to manage this operation retention issue. These background monitoring activities (e.g., read disturb counters and read patrolling) may result in a high refresh rate of data, which increases the write amplification, thus increasing endurance requirements (e.g., the number of write cycles a storage medium can withstand in its lifetime). For example, for a 5 drive write per day (DWPD) application with a warranty of 5 years, the endurance requirement is 18,250 with a write amplification of 2 and roughly 30,000 with a write amplification of 3.3. Further, increased background monitoring activities also degrade performance. As described below, more reliable writes during garbage collection help to reduce the background monitoring activities needed for reliability management, thus increasing performance.

One of the goals of any storage system architecture is to reduce write amplification as much as possible so that available endurance is used to meet storage medium reliability and warranty specifications. Higher system endurance also results in lower cost as the storage system may need less over-provisioning. By reducing the write amplification, the endurance of the storage medium is increased and the overall cost of the storage system is decreased. As described below, more reliable writes during garbage collection help to reduce the frequency of data refreshes due to retention charge loss or read disturb issues, resulting in write amplification reduction and extension of the lifetime of the storage system.

FIG. 2 is a block diagram illustrating an exemplary management module 121, in accordance with some embodiments. Management module 121 typically includes one or more processing units (CPUs) 122 for executing modules, programs and/or instructions stored in memory 206 and thereby performing processing operations, memory 206, and one or more communication buses 208 for interconnecting these components. Communication buses 208 optionally include circuitry (sometimes called a chipset) that interconnects and controls communications between system components. Management module 121 is coupled to host interface 129, additional module(s) 125, and storage medium I/O 128 by communication buses 208. Memory 206 includes high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. Memory 206 optionally includes one or more storage devices remotely located from the CPU(s) 122. Memory 206, or alternately the non-volatile memory device(s) within memory 206, comprises a non-transitory computer readable storage medium. In some embodiments, memory 206, or the computer readable storage medium of memory 206 stores the following programs, modules, and data structures, or a subset thereof:

• • a data read module 216 that is used for reading data from one or more blocks in a storage medium;
  • a data write module 218 that is used for writing data to one or more blocks in a storage medium;
  • a data erase module 220 that is used for erasing data from one or more blocks in a storage medium;
  • a translation table 222 that is used for mapping logical addresses to physical addresses; and
  • a garbage collection module 224 that is used for garbage collection for one or more blocks in a storage medium.

In some embodiments, the garbage collection module 224 optionally includes the following modules or sub-modules, or a subset thereof:

• • a garbage collection read module 226 that is used for reading data from one or more blocks in a storage medium during a garbage collection operation;
  • a garbage collection write module 228 that is used for writing data to one or more blocks in a storage medium during a garbage collection operation;
  • a garbage collection erase module 230 that is used for erasing data from one or more blocks in a storage medium during a garbage collection operation;
  • a delay module 232 that is used for delaying enabling read access to one or more write units of a storage medium block; and
  • an update module 234 that is used for updating a translation table (e.g., translation table 222).

Each of the above identified elements may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 206 may store a subset of the modules and data structures identified above. Furthermore, memory 206 may store additional modules and data structures not described above. In some embodiments, the programs, modules, and data structures stored in memory 206, or the computer readable storage medium of memory 206, provide instructions for implementing any of the methods described below with reference to FIGS. 7-8.

Although FIG. 2 shows a management module 121, FIG. 2 is intended more as functional description of the various features which may be present in a management module than as a structural schematic of the embodiments described herein. In practice, and as recognized by those of ordinary skill in the art, items shown separately could be combined and some items could be separated.

As discussed below with reference to FIG. 3A, a single-level flash memory cell (SLC) stores one bit (“0” or “1”). Thus, the storage density of a SLC memory device is one bit of information per memory cell. A multi-level flash memory cell (MLC), however, can store two or more bits of information per cell by using different ranges within the total voltage range of the memory cell to represent a multi-bit bit-tuple. In turn, the storage density of a MLC memory device is multiple-bits per cell (e.g., two bits per memory cell).

FIG. 3A is a simplified, prophetic diagram of voltage distributions 300a found in a single-level flash memory cell (SLC) over time, in accordance with some embodiments. The voltage distributions 300a shown in FIG. 3A have been simplified for illustrative purposes. In this example, the SLC's voltage range extends approximately from a voltage, V_SS, at a source terminal of an NMOS transistor to a voltage, V_DD, at a drain terminal of the NMOS transistor. As such, voltage distributions 300a extend between V_SS and V_DD.

Sequential voltage ranges 301 and 302 between source voltage V_SS and drain voltage V_DD are used to represent corresponding bit values “1” and “0,” respectively. Each voltage range 301, 302 has a respective center voltage V₁ 301b, V₀ 302b. As described below, in many circumstances the memory cell current sensed in response to an applied reading threshold voltages is indicative of a memory cell voltage different from the respective center voltage V₁ 301b or V₀ 302b corresponding to the respective bit value written into the memory cell. Errors in cell voltage, and/or the cell voltage sensed when reading the memory cell, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the memory cell and the time a read operation is performed to read the data stored in the memory cell. For ease of discussion, these effects are collectively described as “cell voltage drift.” Each voltage range 301, 302 also has a respective voltage distribution 301a, 302a that may occur as a result of any number of a combination of error-inducing factors, examples of which are identified above.

In some implementations, a reading threshold voltage V_R is applied between adjacent center voltages (e.g., applied proximate to the halfway region between adjacent center voltages V₁ 301b and V₀ 302b). Optionally, in some implementations, the reading threshold voltage is located between voltage ranges 301 and 302. In some implementations, reading threshold voltage V_R is applied in the region proximate to where the voltage distributions 301a and 302a overlap, which is not necessarily proximate to the halfway region between adjacent center voltages V₁ 301b and V₀ 302b.

In order to increase storage density in flash memory, flash memory has developed from single-level (SLC) cell flash memory to multi-level cell (MLC) flash memory so that two or more bits can be stored by each memory cell. As discussed below with reference to FIG. 3B, a MLC flash memory device is used to store multiple bits by using voltage ranges within the total voltage range of the memory cell to represent different bit-tuples. A MLC flash memory device is typically more error-prone than a SLC flash memory device created using the same manufacturing process because the effective voltage difference between the voltages used to store different data values is smaller for a MLC flash memory device. Moreover, due to any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history, and/or write-read circuitry, a typical error includes a stored voltage level in a particular MLC being in a voltage range that is adjacent to the voltage range that would otherwise be representative of the correct storage of a particular bit-tuple. As discussed in greater detail below with reference to FIG. 3B, the impact of such errors can be reduced by gray-coding the data, such that adjacent voltage ranges represent single-bit changes between bit-tuples.

FIG. 3B is a simplified, prophetic diagram of voltage distributions 300b found in a multi-level flash memory cell (MLC) over time, in accordance with some embodiments. The voltage distributions 300b shown in FIG. 3B have been simplified for illustrative purposes. The cell voltage of a MLC approximately extends from a voltage, V_SS, at the source terminal of a NMOS transistor to a voltage, V_DD, at the drain terminal. As such, voltage distributions 300b extend between V_SS and V_DD.

Sequential voltage ranges 311, 312, 313, 314 between the source voltage V_SS and drain voltages V_DD are used to represent corresponding bit-tuples “11,” “01,” “00,” “10,” respectively. Each voltage range 311, 312, 313, 314 has a respective center voltage 311b, 312b, 313b, 314b. Each voltage range 311, 312, 313, 314 also has a respective voltage distribution 311a, 312a, 313a, 314a that may occur as a result of any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history (e.g., number of program-erase (PE) cycles), and/or imperfect performance or design of write-read circuitry.

Ideally, during a write operation, the charge on the floating gate of the MLC would be set such that the resultant cell voltage is at the center of one of the ranges 311, 312, 313, 314 in order to write the corresponding bit-tuple to the MLC. Specifically, the resultant cell voltage would be set to one of V₁₁ 311b, V₀₁ 312b, V₀₀ 313b and V₁₀ 314b in order to write a corresponding one of the bit-tuples “11,” “01,” “00” and “10.” In reality, due to the factors mentioned above, the initial cell voltage may differ from the center voltage for the data written to the MLC.

Reading threshold voltages V_RA, V_RB and V_RC are positioned between adjacent center voltages (e.g., positioned at or near the halfway point between adjacent center voltages) and, thus, define threshold voltages between the voltage ranges 311, 312, 313, 314. During a read operation, one of the reading threshold voltages V_RA, V_RB and V_RC is applied to determine the cell voltage using a comparison process. However, due to the various factors discussed above, the actual cell voltage, and/or the cell voltage received when reading the MLC, may be different from the respective center voltage V₁₁ 311b, V₀₁ 312b, V₀₀ 313b or V₁₀ 314b corresponding to the data value written into the cell. For example, the actual cell voltage may be in an altogether different voltage range, strongly indicating that the MLC is storing a different bit-tuple than was written to the MLC. More commonly, the actual cell voltage may be close to one of the read comparison voltages, making it difficult to determine with certainty which of two adjacent bit-tuples is stored by the MLC.

Errors in cell voltage, and/or the cell voltage received when reading the MLC, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the MLC and the time a read operation is performed to read the data stored in the MLC. For ease of discussion, sometimes errors in cell voltage, and/or the cell voltage received when reading the MLC, are collectively called “cell voltage drift.”

One way to reduce the impact of a cell voltage drifting from one voltage range to an adjacent voltage range is to gray-code the bit-tuples. Gray-coding the bit-tuples includes constraining the assignment of bit-tuples such that a respective bit-tuple of a particular voltage range is different from a respective bit-tuple of an adjacent voltage range by only one bit. For example, as shown in FIG. 3B, the corresponding bit-tuples for adjacent ranges 301 and 302 are respectively “11” and “01,” the corresponding bit-tuples for adjacent ranges 302 and 303 are respectively “01” and “00,” and the corresponding bit-tuples for adjacent ranges 303 and 304 are respectively “00” and “10.” Using gray-coding, if the cell voltage drifts close to a read comparison voltage level, the error is typically limited to a single bit within the 2-bit bit-tuple.

The following describes an example in which q=2 (i.e., 2 bits per cell in a MLC flash memory). However, those skilled in the art will appreciate that the 2-bit implementation may be extended to other types of MLC flash memory that have more bits (q≧3) per memory cell.

With respect to MLC flash memory (e.g., storage media 130, FIG. 1), there are generally two types of read operations that may be performed on MLC flash. One is a single-page read, which includes reading the respective bits of a particular page from a number of q-page MLC flash memory cells. For example, for a 2-page flash memory, the two constituent pages are referred to as the lower page and the upper page, where the lower page bit is typically the least significant bit of the 2-bit bit-tuple, and the upper page is the most significant bit. For the single-page read scenario, one of the upper page and lower page bit from a number of MLC flash memory cells is read. Thus, a lower-page read delivers a sequence of respective lower-page bits from a number of 2-page MLC flash memory cells. The other type of read is a joint-page read, which generally includes reading the respective bits of two or more pages from a number of q-page MLC flash memory cells. So, for a 2-page (i.e., q=2) flash memory, a joint-page read delivers a sequence of respective 2-bit bit-tuples from a number of 2-page MLC flash memory cells.

Similarly, with respect to MLC flash memory, there are generally two types of write operations that may be performed on MLC flash. One is a single-page write, which includes programming the respective bits of a particular page from a number of q-page MLC flash memory cells. For example, for a 2-page flash memory, a lower-page write operation programs the lower page bits of the memory cells and an upper-page write operation programs the upper page bits of the memory cells. The other type of write is a joint-page write, which generally includes programming the respective bits of two or more pages for a number of q-page MLC flash memory cells. So, for a 2-page (i.e., q=2) flash memory, a joint-page write programs both the lower page and upper page bits. As discussed below with respect to FIGS. 4A-4B, in some embodiments, joint-page writes include a coarse multi-bit write operation and/or a second (e.g., fine) multi-bit write operation.

Using the example of a 2-page flash memory, in some embodiments, a coarse/fine programming scheme programs both the lower page and the upper page in a first (e.g., coarse) multi-bit write operation that partially programs each memory cell of a respective write unit, and then programs both the lower page and the upper page in a second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit. In some embodiments, FIG. 4A illustrates voltage distributions found in a memory cell after the first (e.g., coarse) multi-bit write operation, and FIG. 4B illustrates voltage distributions found in a memory cell after the second (e.g., fine) multi-bit write operation.

FIG. 4A is a prophetic diagram of voltage distributions 400a found in a multi-level flash memory cell (MLC) after a coarse multi-bit programming operation, in accordance with some embodiments. The voltage distributions 400a shown in FIG. 4A have been simplified for illustrative purposes. The cell voltage of a MLC approximately extends from a voltage, V_SS, at the source terminal of a NMOS transistor to a voltage, V_DD, at the drain terminal. As such, voltage distributions 400a extend between V_SS and V_DD.

Sequential voltage ranges 401, 402, 403, 404 between the source voltage V_SS and drain voltages V_DD are used to represent corresponding values “erase,” “A,” “B,” “C,” respectively. Each voltage range 401, 402, 403, 404 has a respective center voltage 401b, 402b, 403b, 404b. Each voltage range 401, 402, 403, 404 also has a respective voltage distribution 401a, 402b, 403a, 404a that may occur as a result of any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history (e.g., number of program-erase (PE) cycles), and/or imperfect performance or design of write-read circuitry.

Ideally, during a write operation, the charge on the floating gate of the MLC would be set such that the resultant cell voltage is at the center of one of the ranges 401, 402, 403, 404 in order to write the corresponding value to the MLC. Specifically, the resultant cell voltage would be set to one of V_erase 401b, V_A 402b, V_B 403b and V_C 404b in order to write a corresponding one of the values “erase,” “A,” “B,” and “C.” In reality, due to the factors mentioned above, the initial cell voltage may differ from the center voltage for the data written to the MLC.

Reading threshold voltages V_RA, V_RB and V_RC are positioned between adjacent center voltages (e.g., positioned at or near the halfway point between adjacent center voltages) and, thus, define threshold voltages between the voltage ranges 401, 402, 403, 404. During a read operation, one of the reading threshold voltages V_RA, V_RB and V_RC is applied to determine the cell voltage using a comparison process. However, due to the various factors discussed above, the actual cell voltage, and/or the cell voltage received when reading the MLC, may be different from the respective center voltage V_erase 401b, V_A 402b, V_B 403b or V_C 404b corresponding to the data value written into the cell. For example, the actual cell voltage may be in an altogether different voltage range, strongly indicating that the MLC is storing a different value than was written to the MLC. More commonly, the actual cell voltage may be close to one of the read comparison voltages, making it difficult to determine with certainty which of two adjacent values is stored by the MLC.

In some embodiments, the impact of a cell voltage drifting from one voltage range to an adjacent voltage range is reduced by further programming the bits (e.g., with a fine multi-bit programming operation) such that there is less overlap between voltage distributions 401a, 402b, 403a, 404a, as discussed below with respect to FIG. 4B.

FIG. 4B is a prophetic diagram of voltage distributions found in a multi-level flash memory cell (MLC) after a fine multi-bit programming operation, in accordance with some embodiments. Explanations provided above in connection with FIG. 4A, with respect to voltage distributions 400a, sequential voltage ranges 401, 402, 403, and 404, center voltages V_erase 401b, V_A 402b, V_B 403b and V_C 404b, voltage distributions 401a, 402b, 403a, and 404a, and reading threshold voltages V_RA, V_RB and V_RC are equally applicable to voltage distributions 400b, sequential voltage ranges 411, 412, 413, and 414, center voltages V_erase 411b, V_A 412b, V_B 413b and V_C 414b, voltage distributions 411a, 412a, 413a, and 414a, and reading threshold voltages V_RA, V_RB and V_RC as shown in FIG. 4B, except as described next.

After a fine multi-bit programming operation, as in FIG. 4B, the overlap between voltage distributions 411a, 412b, 413a, and 414a is less than the overlap between voltage distributions after a coarse multi-bit programming operation (e.g., voltage distributions 401a, 402b, 403a, and 404a, FIG. 4A). In some embodiments, the fine multi-bit programming operation occurs after a coarse multi-bit programming operation. The result of this coarse/fine programming scheme is much narrower voltage distributions and more margins between values “erase,” “A,” “B,” and “C,” which results, in turn, in reduced error rates, increased correction capability, and reduced usage of secondary error recovery or other techniques for recovering data that would otherwise have been lost. Further, data in the memory cell does not need to be refreshed as often, because the error rate is reduced, which results in reduced write amplification. The main drawback of a coarse/fine programming scheme is that the technique is not ideal for a write operation performed in response to a host command due to performance reasons. For example, coarse/fine programming takes longer than lower page/upper page programming for the same amount of data. This increases latency and impacts write performance. Thus, in some embodiments, a lower page/upper page programming scheme is used during write operations performed in response to a host command, as discussed below with respect to FIGS. 5A-5B. However, using a coarse/fine programming scheme during a garbage collection operation enables more reliable writes for the data that is re-written during garbage collection, thus reducing write amplification and extending the lifetime of the storage system.

Using the example of a 2-page flash memory, in some embodiments, a lower page/upper page programming scheme programs the lower page in a first (e.g., lower page) write operation that partially programs each memory cell of a respective write unit with a single, respective lower page bit, and then programs the upper page in a second (e.g., upper page) write operation that completes programming of each memory cell of the respective write unit with a respective upper page bit. In some embodiments, FIG. 5A illustrates voltage distributions found in a memory cell after the first (e.g., lower page) write operation, and FIG. 5B illustrates voltage distributions found in a memory cell after the second (e.g., upper page) write operation.

FIG. 5A is a prophetic diagram of voltage distributions found in a multi-level flash memory cell (MLC) after a lower page programming operation, in accordance with some embodiments. The voltage distributions 500a shown in FIG. 5A have been simplified for illustrative purposes. The cell voltage of a MLC approximately extends from a voltage, V_SS, at the source terminal of a NMOS transistor to a voltage, V_DD, at the drain terminal. As such, voltage distributions 500a extend between V_SS and V_DD.

Sequential voltage ranges 501 and 502 between the source voltage V_SS and drain voltages V_DD are used to represent corresponding values “erase” and “LM” (e.g., lower page mode programming) respectively. Each voltage range 501 and 502 has a respective center voltage 501b and 502b. Each voltage range 501 and 502 also has a respective voltage distribution 501a and 502b that may occur as a result of any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history (e.g., number of program-erase (PE) cycles), and/or imperfect performance or design of write-read circuitry.

Ideally, during a write operation, the charge on the floating gate of the MLC would be set such that the resultant cell voltage is at the center of one of the ranges 501 and 502 in order to write the corresponding value to the MLC. Specifically, the resultant cell voltage would be set to one of V_erase 501b or V_LM 502b in order to write a corresponding one of the values “erase” or “LM.” In reality, due to the factors mentioned above, the initial cell voltage may differ from the center voltage for the data written to the MLC.

FIG. 5B is a prophetic diagram of voltage distributions found in a multi-level flash memory cell (MLC) after an upper page programming operation, in accordance with some embodiments. Explanations provided above in connection with FIG. 4A, with respect to voltage distributions 400a, sequential voltage ranges 401, 402, 403, and 404, center voltages V_erase 401b, V_A 402b, V_B 403b and V_C 404b, voltage distributions 401a, 402b, 403a, and 404a, and reading threshold voltages V_RA, V_RB and V_RC are equally applicable to voltage distributions 500b, sequential voltage ranges 511, 512, 513, and 514, center voltages V_erase 511b, V_A 512b, V_B 513b and V_C 514b, voltage distributions 511a, 512a, 513a, and 514a, and reading threshold voltages V_RA, V_RB and V_RC as shown in FIG. 5B, except as described next.

After a lower page programming operation programs the lower page bit, as discussed above with respect to FIG. 5A, an upper page programming operation programs the upper page bit. Thus, the two voltage distributions 501a and 502a (FIG. 5A) become four voltage distributions 511a, 512a, 513a, and 514a (FIG. 5B).

FIG. 6 illustrates a sequence 600 of programming pages in a coarse/fine programming scheme, in accordance with some embodiments. In some embodiments, FIG. 6 relates to the order of operations for writing to memory cells during a garbage collection operation, as discussed below with respect to operation 804. Typically, memory cells are written in a predefined sequence (e.g., first word line to last word line) and in general, a word line is not written to again until the block containing that word line is erased. Here, WL_N (e.g., word line N) 602 is programmed by a coarse multi-bit programming operation (e.g., Coarse (0)). Then, WL_N+1 (e.g., word line N+1) 604 is programmed by a coarse multi-bit programming operation (e.g., Coarse (1)). Next, WL_N 602 is programmed again, this time by a fine multi-bit programming operation (e.g., Fine (2)). The order of operations continues in this manner for the remaining word lines WL_N+2 606, WL_N+3 608, WL_N+4 610, etc. In this example, each coarse programming operation, other than the coarse programming operation on the first word line, is followed by a fine programming operation on the word line prior to the word line on which the coarse programming operation was performed. In addition, each fine programming operation (e.g., on word line N), excluding the fine programming operations on the last two word lines of the set of word lines being programmed, is followed by a coarse programming operation on a word line (e.g., on word line N+2) positioned two word lines after the word line on which the fine programming operation was performed.

Technically, a translation table (e.g., translation table 222, FIG. 2) can be updated for a given word line upon successful completion of the coarse and fine programming on that word line. For example, the translation table can be updated for WL_N 602 upon successful completion of Coarse (0) and Fine (2). However, in some embodiments, to allow for more reliable reads, a translation table is updated after two sequentially adjacent word lines have completed programming. For example, the translation table is updated for WL_N 602 after WL_N+1 604 and WL_N+2 606 have completed programming (e.g., upon successful completion of Coarse (1), Fine (4), Coarse (3), and Fine (6). This reduces coupling effects and makes the read for WL_N 602 more reliable. Optionally, in some embodiments, a translation table is updated after all remaining word lines in the block have completed programming.

FIG. 7 illustrates a flowchart representation of a method 700 of garbage collection in a storage system, in accordance with some embodiments. As noted above with respect to FIG. 1, since erasure of a storage medium is performed on a block basis, but in many embodiments, programming of the storage medium is performed on a smaller subunit of a block (e.g., on a page basis), pages with invalid data cannot be overwritten until the whole block containing those pages is erased. The storage system (e.g., data storage system 100, FIG. 1) uses garbage collection to reclaim portions of memory (e.g., storage medium 130, FIG. 1) that no longer contain valid data, which initiates performance of method 700.

At least in some implementations, method 700 is performed by a storage system (e.g., data storage system 100, FIG. 1) or one or more components of the storage system (e.g., memory controller 120 and/or storage medium 130, FIG. 1). In some embodiments, method 700 is governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors of a device, such as the one or more processing units (CPUs) 122 of management module 121, shown in FIGS. 1 and 2.

A storage system (e.g., data storage system 100, FIG. 1), during a garbage collection operation, while writing data to a sequence of write units of a storage medium block (e.g., selectable portion of storage medium 131, FIG. 1), delays (702) enabling read access to a respective write unit of the storage medium block, to which data was written during garbage collection, until a predefined subsequent operation on the storage medium block has been completed. In some implementations, a delay module (e.g., delay module 232, FIG. 2) is used to delay enabling read access to the respective write unit of the storage medium block, as described above with respect to FIG. 2.

In some embodiments, the predefined subsequent operation on the storage medium block comprises (704) completion of writing data to at least N write units subsequent to writing data to the respective write unit. In some embodiments, the write units are word lines. For example, if a write unit is a word line and N is equal to 2, the predefined subsequent operation on the storage medium block comprises completion of writing data to at least 2 word lines subsequent to writing data to the respective word line. Again, if the write unit is a word line and N is equal to 2, using the word lines from FIG. 6 as an example, the storage system delays enabling read access to WL_N 602, to which data was written during garbage collection, until completion of writing data to WL_N+1 604 and WL_N+2 606. Although word lines were used as an example here, in other embodiments, the write units are pages, or other units that can be programmed by a storage system. It is noted that the write units in method 700 need not be the minimum size write units of the physical storage devices to which data is being written. Thus, in some embodiments, the write units for method 700 are word lines, but the minimum size write unit of the physical storage devices is a page or other unit smaller than a complete word line.

In some embodiments, the predefined subsequent operation on the storage medium block comprises (706) completion of writing data to all remaining write units of the storage medium block subsequent to writing data to the respective write unit. Using FIG. 6 as an example, the storage system delays enabling read access to WL_N 602, to which data was written during garbage collection, until completion of writing data to all remaining word lines of the storage medium block. In some embodiments, the storage system delays enabling read access to a first page of a storage medium block, to which data was written during garbage collection, until completion of writing data to all remaining pages of the storage medium block subsequent to writing data to the first page.

In some embodiments, the sequence of write units is (708) on a sequence of word lines. In some embodiments, write units are pages and the sequence of pages is on a sequence of word lines. For example, if a word line has two pages (e.g., a lower page and an upper page), data may be written to the sequence of pages in word line order (e.g., completing programming of the lower page and the upper page of a word line before starting programming of the next word line) or data may be written to the sequence of pages in a zigzag fashion, as described above with respect to FIG. 6.

In some embodiments, the storage medium comprises (710) one or more non-volatile storage devices, such as flash memory devices. In some implementations, the non-volatile storage medium (e.g., storage medium 130, FIG. 1) is a single flash memory device, while in other implementations the non-volatile storage medium includes a plurality of flash memory devices. In some implementations, the non-volatile storage medium (e.g., storage medium 130, FIG. 1) is NAND-type flash memory or NOR-type flash memory.

Optionally, in some embodiments, the storage system (e.g., data storage system 100, FIG. 1) updates (712) a translation table to point to the respective write unit after the predefined subsequent operation on the storage medium block has been completed. For example, if the predefined subsequent operation is writing data to at least 2 write units (e.g., 2 word lines) subsequent to writing data to the respective write unit (e.g., WL_N 602, FIG. 6), the storage system updates a translation table to point to the respective write unit (e.g., WL_N 602, FIG. 6) after completion of writing data to at least 2 write units (e.g., WL_N+1 604 and WL_N+2 606, FIG. 6) subsequent to writing data to the respective write unit. In some implementations, an update module (update module 234, FIG. 2) is used to update the translation table (e.g., translation table 222, FIG. 2), as described above with respect to FIG. 2.

FIG. 8 illustrates a flowchart representation of a method 800 of writing data in a storage system, in accordance with some embodiments. As noted above with respect to FIG. 1, since erasure of a storage medium is performed on a block basis, but in many embodiments, programming of the storage medium is performed on a smaller subunit of a block (e.g., on a page basis), pages with invalid data cannot be overwritten until the whole block containing those pages is erased. The storage system (e.g., data storage system 100, FIG. 1) uses garbage collection to reclaim portions of memory (e.g., storage medium 130, FIG. 1) that no longer contain valid data, which initiates performance of method 800. Alternatively, as noted above with respect to FIG. 1, during a write operation, the storage system (e.g., data storage system 100, FIG. 1) receives data to be stored in a storage medium (e.g., storage medium 130, FIG. 1) from a host (e.g., computer system 110, FIG. 1), which initiates performance of method 800.

At least in some implementations, method 800 is performed by a storage system (e.g., data storage system 100, FIG. 1) or one or more components of the storage system (e.g., memory controller 120 and/or storage medium 130, FIG. 1). In some embodiments, method 800 is governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors of a device, such as the one or more processing units (CPUs) 122 of management module 121, shown in FIGS. 1 and 2.

A storage system (e.g., data storage system 100, FIG. 1), during a garbage collection operation, while writing data to a first sequence of write units of a storage medium block, performs (802) a coarse multi-bit write operation that partially programs each memory cell of a respective write unit with a plurality of bits, followed by a second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit with the plurality of bits. In some embodiments, using a 2-bit (i.e., q=2) memory cell for example, a coarse 2-bit write operation partially programs the lower page and upper page bits of the memory cell. In some embodiments, FIG. 4A illustrates voltage distributions found in a memory cell after the coarse 2-bit write operation. Subsequent to the coarse multi-bit write operation, a second (e.g., fine) multi-bit write operation completes programming of each memory cell of the respective write unit. In some embodiments, using a 2-bit (i.e., q=2) memory cell for example, a second (e.g., fine) 2-bit write operation completes programming of the lower page and upper page bits of the memory cell. In some embodiments, FIG. 4B illustrates voltage distributions found in a memory cell after the second (e.g., fine) 2-bit write operation. In some implementations, a garbage collection write module (e.g., garbage collection write module 228, FIG. 2) is used to write data to the first sequence of write units, as described above with respect to FIG. 2. Although a 2-bit (i.e., q=2) memory cell is used as an example here, the 2-bit implementation may be extended to other types of memory that have more bits (q≧3) per memory cell.

In some embodiments, during the garbage collection operation, the storage system performs (804) a second coarse multi-bit write operation that partially programs each memory cell of another write unit, distinct from the respective write unit, after the coarse programming of the respective write unit and prior to the second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit. For example, as discussed above with respect to FIG. 6, in some embodiments, the storage system performs a second coarse multi-bit write operation (e.g., Coarse (1), FIG. 6) that partially programs another write unit (e.g., WL_N+1 604, FIG. 6), distinct from the respective write unit (e.g., WL_N 602, FIG. 6), after the coarse programming of the respective write unit (e.g., Coarse (0), FIG. 6) and prior to the second (e.g., fine) multi-bit write operation that completes programming of the respective write unit (e.g., Fine (2), FIG. 6). In some implementations, a garbage collection write module (e.g., garbage collection write module 228, FIG. 2) is used to perform write operations, as described above with respect to FIG. 2.

In some embodiments, during the garbage collection operation, the storage system performs two or more write operations on write units distinct from the respective write unit after the coarse programming of a respective write unit and prior to the second (e.g., fine) multi-bit write operation that completes programming of each memory cell of the respective write unit. In the example shown in FIG. 6, the two or more write operations are a fine multi-bit write operation on a prior write unit relative to the respective write unit and a coarse write operation on a subsequent write unit relative to the respective write unit.

In some embodiments, the storage medium comprises (806) one or more non-volatile storage devices, such as flash memory devices, as described above with respect to operation 710 (FIG. 7).

Next, the storage system, during a write operation, performed in response to a host command, while writing data to a second sequence of write units of the storage medium block, performs (808) a lower page write operation that partially programs each memory cell of a respective write unit with a single, respective lower page bit, followed by an upper page write operation that completes programming of each memory cell of the respective write unit with a respective upper page bit. In some embodiments, using a 2-bit (i.e., q=2) memory cell for example, the storage system performs a lower page write operation that partially programs the memory cell with a single lower page bit. In some embodiments, FIG. 5A illustrates voltage distributions found in a memory cell after the lower page write operation. Subsequent to the lower page write operation, the storage system performs an upper page write operation that completes programming of the memory cell with an upper page bit. In some embodiments, FIG. 5B illustrates voltage distributions found in a memory cell after the upper page write operation. In some implementations, a data write module (e.g., data write module 218, FIG. 2) is used to write data to the second sequence of write units, as described above with respect to FIG. 2.

Optionally, when erasing data in the second sequence of write units, the storage system performs (810) a default erase operation. In some embodiments, data that was written to the second sequence of write units was written during a write operation, performed in response to a host command, and lower page/upper page programming was used. The storage system performs a default erase operation when erasing this data. In some implementations, a data erase module (e.g., data erase module 220, FIG. 2) is used to erase data in the second sequence of write units, as described above with respect to FIG. 2.

Optionally, when erasing data in the first sequence of write units, the storage system performs (812) a shallow erase operation having a shorter duration than the default erase operation. In some embodiments, data that was written to the first sequence of write units was written during a garbage collection operation, and coarse/fine programming was used. As a result of using coarse/fine programming, the voltage distributions are tighter (e.g., compared to voltage distributions from lower page/upper page programming) and a shallow erase operation may be used. In some embodiments, a shallow erase operation has a shorter duration than the default erase operation. In some embodiments, a shallow erase operation reduces stress on (e.g., causes less damage to) the tunnel oxide of the floating gate transistor than the default erase operation, which translates to higher reliability of the memory cells. In some implementations, a garbage collection erase module (e.g., garbage collection erase module 230, FIG. 2) is used to erase data in the first sequence of write units, as described above with respect to FIG. 2.

In some implementations, with respect to any of the methods described above, the storage medium (e.g., storage medium 130, FIG. 1) is a single flash memory device, while in other implementations, the storage medium (e.g., storage medium 130, FIG. 1) includes a plurality of flash memory devices.

In some implementations, with respect to any of the methods described above, a storage system includes a storage medium (e.g., storage medium 130, FIG. 1), one or more processors (e.g., CPUs 122, FIGS. 1 and 2) and memory (e.g., memory 206, FIG. 2) storing one or more programs configured for execution by the one or more processors and configured to perform or control performance of any of the methods described above.

In some implementations, with respect to any of the methods described above, a device operable to perform garbage collection and/or operable to write data includes a storage medium interface (e.g., storage medium I/O 128, FIG. 1) for coupling the device to the storage medium (e.g., storage medium 130, FIG. 1) and one or more modules, including a memory management module (e.g., management module 121, FIGS. 1 and 2) that includes one or more processors (e.g., CPUs 122, FIGS. 1 and 2) and memory (e.g., memory 206, FIG. 2) storing one or more programs configured for execution by the one or more processors, the one or more modules coupled to the storage medium interface (e.g., storage medium I/O 128, FIG. 1) and configured to perform or control performance of any of the methods described above.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the “first contact” are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.

The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.

Claims

1. A method of garbage collection in a storage system, the method comprising: performing a garbage collection operation, including: writing data, for the garbage collection operation, to a sequence of write units of a non-volatile storage medium block that was erased prior to writing data to the sequence of write units, including: writing data to a first write unit of the storage medium block; andafter writing data to the first write unit, writing data to at least N write units of the storage medium block, the at least N write units of the storage medium block including a second write unit of the storage medium block, wherein N is a positive integer;after writing data to the at least N write units, enabling read access to the first write unit;writing data to a subsequent write unit of the storage medium block; andafter writing data to the subsequent write unit, enabling read access to the second write unit.

2. The method of claim 1, further comprising deferring updating a translation table to point to the first write unit until after writing data to the at least N write units has been completed.

3. The method of claim 1, wherein the sequence of write units is on a sequence of word lines.

4. The method of claim 1, wherein the storage medium comprises one or more flash memory devices.

5. A device operable to perform garbage collection for a storage medium, the device comprising: a storage medium interface for coupling the device to the storage medium; andone or more modules, including a memory management module that includes one or more processors and memory storing one or more programs configured for execution by the one or more processors, the one or more modules coupled to the storage medium interface and configured to: perform a garbage collection operation, including: writing data, for the garbage collection operation, to a sequence of write units of a non-volatile storage medium block that was erased prior to writing data to the sequence of write units, including: writing data to a first write unit of the storage medium block; andafter writing data to the first write unit, writing data to at least N write units of the storage medium block, the at least N write units of the storage medium block including a second write unit of the storage medium block, wherein N is a positive integer;after writing data to the at least N write units, enabling read access to the first write unit;writing data to a subsequent write unit of the storage medium block; andafter writing data to the subsequent write unit, enabling read access to the second write unit.

6. The device of claim 5, wherein the one or more modules are further configured to defer updating a translation table to point to the first write unit until after writing data to the at least N write units has been completed.

7. The device of claim 5, wherein the sequence of write units is on a sequence of word lines.

8. The device of claim 5, wherein the storage medium comprises one or more flash memory devices.

9. A non-transitory computer readable storage medium storing one or more programs configured for execution by a device coupled to a storage medium, the one or more programs comprising instructions for causing the device to: perform a garbage collection operation, including: writing data, for the garbage collection operation, to a sequence of write units of a non-volatile storage medium block that was erased prior to writing data to the sequence of write units, including: writing data to a first write unit of the storage medium block; andafter writing data to the first write unit, writing data to at least N write units of the storage medium block, the at least N write units of the storage medium block including a second write unit of the storage medium block, wherein N is a positive integer;after writing data to the at least N write units, enabling read access to the first write unit;writing data to a subsequent write unit of the storage medium block; andafter writing data to the subsequent write unit, enabling read access to the second write unit.

10. The non-transitory computer readable storage medium of claim 9, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the device to defer updating a translation table to point to the first write unit until after the writing data to the at least N write units has been completed.

11. The non-transitory computer readable storage medium of claim 9, wherein the sequence of write units is on a sequence of word lines.

12. The non-transitory computer readable storage medium of claim 9, wherein the storage medium comprises one or more flash memory devices.

13. The method of claim 1, wherein N is at least two.

14. The device of claim 5, wherein N is at least two.

15. The non-transitory computer readable storage medium of claim 9, wherein N is at least two.