Brian Dipert and Markus Levy “Designing with Flash Memory—The definitive guide to designing flash memory hardware and software for components and PCMCIA cards”, Annabooks, ISBN 0-929392-17-5, Ch. 3, pp. 23-44. |
AMD, Technology Background brochure, “3.0 Volt-only Page Mode Flash Memory Technology.” |
AMD, Technology Background brochure, “3.0 Volt-only Burst Mode Flash Memory Technology.” |
AMD, Technology Background brochure, “1.8 Volt-only Flash Memory Technology.” |
AMD, Technology Background brochure, “AMD DL160 and DL320 Series Flash: New Densities, New Features.” |
Intel Corporation, “Common Flash Memory Interface Specification”, Release 1.1, May 30, 1997. |
AMD, “Common Flash Memory Interface Publication 100—Vendor & Device ID Code Assignments”, Jul. 25, 1996, vol. 96.1. |
AMD “Am29DL162C/AM29DL163C 16 Megabit (2 M×8-Bit/1 M×16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory”, Publication 21533, Rev: C Amendment/+2, Jul. 14, 1999. |
Intel Corporation, “1.8 Volt Intel® Dual-Plane Flash Memory 28F320D18 (×16)”, Product Review Datasheet, Order No.: 290672-002, Oct. 1999. |
Macronix International Co., Ltd. “MXIC Advance Information MX29VW160T/B—16M-Bit [2M×8-Bit/1M×16-Bit]Simultaneous Read/Write Single 2.5V Operation Flash Memory”, P/N:PM0567, Rev. 0.8, May 17, 1999. |
ATMEL Corporation, “ATMEL® 16-megabit (1M×16/2M×8) 3-volt Only Flash Memory”, Rev. 0925H-08/99. |
STMicroelectronics, “M59DR032A, M59DR032B, 32 Mbit (2Mb×16, Dual Bank, Page) Low Voltage Flash memory”, preliminary date, Oct. 1999, pp. 1-38. |
“AMD—Flash Introduction”, obtained at the internet address http://www.amd.com/products/nvd/overview/flash_intro.html, Apr. 14, 1999. |
“AMD—Simultaneous Read/Write”, obtained at the internet address http://www.amd.com/products/nvd/overview/simuintro.html, Jul. 12, 1999. |
“AMD News Release #9879”, obtained at the internet address http://www.amd.com/news/prodpr/9879.html. |
“Intel® 1.8 Volt Dual-Plane 32-Mbit Flash Memory (D18)”, obtained at the internet address http:///www.intel.com/design/flcomp/prodbref/298131.htm, Nov. 18, 1999. |
U.S. Patent Application, Serial No. 09/159, 023, filed Sep. 23, 1998. |
U.S. Patent Application, Serial No. 09/159,142, filed Sep. 23, 1998. |
U.S. Patent Application, Serial No. 09/159, 489, filed Sep. 23, 1998. |
Bernd Laquai, Harald Richter, Bernd Hofflinger, “A New Method and Test Structure for Easy Determination of Femoto-Farad On-Chip Capacitances in a Mos Process”, Proc. IEEE 1992 Int. Conference on Microelectronic Test Structures, vol. 5, March 1992, pp. 62-66. |
C. Kortekaas, “On-Chip Quasi-Static Floating-Gate Capacitance Measurement Method”, Proc. IEEE 1990 Int. Conference on Microelectronic Test Structures, vol. 3, March 1990, pp. 109-113. |
Bruce W. McGaughy, James C. Chen, Dennis Sylvester, Chenming Hu, “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement”, IEEE Electron Device Letter, vol. 18, No. 1, January 1997, pp. 21-23. |
Bruce W. McGaughy, James C. Chen, Dennis Sylvester, Chenming Hu, “An On-Chip Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique”, IEEE Tech. Digest International Electron Devices Meeting, December 1996. |
Dennis Sylvester, James C. Chen, Chenming Hu, “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and 3-D Simulation”, IEEE 1997 Custom Integrated Circuits Conference, pp. 491-494. |
Dennis Sylvester, James C. Chen, Chenming Hu, “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three-Dimensional Simulation”, IEEE Journal of Solid-State Circuits, vol. 33, No. 3, March 1998, pp. 449-453. |
Dennis Sylvester, James C. Chen, Chenming Hu, “An On-Chip, Interconnect Capacitance Charcterization Method with Sub-Femto-Farad Resolution”, IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 2, May 1998, pp. 204-210. |
Dennis Sylvester, Chenming Hu, Sam O. Nakagawa, “Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs”, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 42-43. |
Samuel O. Nakagawa, Dennis M. Sylvester, John McBride, Soo-Young Oh, “On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSI Interconnect”, August 1998, The Hewlett-Packard Journal, pp. 39-45. |
A. Khalkhal, P. Nouet, “On-Chip Measurement of Interconnect Capacitances in a CMOS Process”, Proc. IEEE 1995 Int. Conference on Microeletronic Test Structures, vol. 8, March 1995, pp. 145-149. |
G.J. Gaston and I.G. Daniels, “Efficient Extraction of Metal Parasitic Capacitances”, Proc. IEEE 1995 Int. Conference on Microelectronic Test Structures, vol. 8, March 1995. pp. 157-160. |
AMD Internal Correspondence, “CS44E6 Test Chip Electrical ILD Capacitance Measurement Tile”, Oct. 20, 1997. |