The present invention is related to co-pending patent application Ser. No. 09/222,143, entitled “X-Y Grid Tree Tuning Method,” by Restle et al., filed of even date herewith. This co-pending application and the present invention are commonly assigned to the International Business Machines Corporation, Armonk, N.Y. This co-pending application is hereby incorporated by reference in its entirety into the present application.
Number | Name | Date | Kind |
---|---|---|---|
5109168 | Rusu | Apr 1992 | |
5163068 | El-Amawy | Nov 1992 | |
5430397 | Itoh et al. | Jul 1995 | |
5537498 | Bausman et al. | Jul 1996 | |
5557779 | Minami | Sep 1996 | |
5638291 | Li et al. | Jun 1997 | |
5656963 | Masleid et al. | Aug 1997 | |
5668484 | Nomura | Sep 1997 | |
5668490 | Mitra et al. | Sep 1997 | |
5880607 | Mitra | Mar 1999 | |
6006025 | Cook et al. | Dec 1999 | |
6088254 | Kernami | Jul 2000 | |
6157237 | Mitra | Dec 2000 |
Entry |
---|
N. Menezes et al., Skew Reduction in Clock Trees Using Wire Width Optimization, 1993 Custom Integrated Circuits Conference, pp. 9.6.1-9.6.4, May 1993.* |
K. Yip, Clock Tree Distribution, IEEE Potentials, pp. 11-14, Apr. 1997.* |
M. Nekili et al., Pipelined H-Trees for High-Speed Clocking of Large Integrated Systems in Presence of Process Variations, IEEE Transactions on VLSI Systems, pp. 161-174, Jun. 1997.* |
C. L. Ratzlaff et al., “RICE: Rapid Interconnect Circuit Evaluation Using AWE,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 6, Jun. 1994, pp. 763-776. |
P. J. Restle et al., “Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1998, pp. 662-665. |