The present invention is related to a novel line driver for applications such as ADSL (Asymmetric Digital Subscriber Line) or VDSL (Very High Speed Digital Subscriber Line).
In the design of line drivers for applications such as ADSL (Asymmetric Digital Subscriber Line) or VDSL (Very High Speed Digital Subscriber Line), power consumption is a critical issue and signal linearity requirements are stringent. Manufacturers are continually looking for solutions to decrease power consumption. At the moment, the DSL chip market is estimated at 50 million chip sets for 2000 (total value of more than 1 billion USD in 2000).
A traditional class G driver consumes about 1.3 Watt to produce an output signal of 100 mWatt. The power consumption of the class G driver may be reduced by about 100 mWatt/η (where η is the efficiency of the amplifier which typically has a value between 0.05 and 0.10) through use of an active back termination. Such an active back terminated line driver is described in EP-A-0901221.
A class 0 driver can also be used, including switches and circuitry to monitor the crest factor of the transmitted signal and to appropriately switch between two power supply levels.
A traditional switch mode driver (SW-DRIVER), which consists of a ΣΔ-modulator (ΣΔ), circuitry (SW) to monitor the crest factor of the transmitted signal and to appropriately switch between different power supply levels, a low pass filter (Fl) and a hybrid (HY), less power as digital technology proceeds to deeper submicron technologies. Such a switch mode driver for instance is shown in
A switch mode amplifier (digital amp.) in parallel with a linear amplifier (analog amp.) each producing part of an outputted audio signal is disclosed in
The switching mode line driver (SW-DRIVER) is the most power efficient line driver, but is very sensitive for power supply variations (low power supply rejection) and clock jitter. This results in errors in the transmitted signal.
The present invention aims to provide a novel line driver which is linear, stable, and efficient. The output of said driver should be free of errors due to power supply variations and clock jitter.
The present invention concerns a line driver for amplifying an input signal, said line driver comprising:
The present invention equally concerns a line driver for amplifying an input signal, said line driver comprising:
In a line driver according to the present invention, the proportion of the first output signal in the total output signal is preferably at least 95%.
The line driver of the invention can comprise a digital to analogue converter arranged to convert the input signal to an analogue input signal and that said analogue input signal is fed to the second input terminal of the linear amplifier.
Preferably, the linear amplifier is selected from the group consisting of class A and class A/B amplifiers, and the non-linear amplifier is preferably selected from the group consisting of switching mode amplifiers, clipping amplifiers, class B, G or K amplifiers and pulse width modulation amplifiers.
The combining means can comprise e.g. a hybrid. The input signal can be generated by a DMT.
In an advantageous embodiment of the present invention, the line driver further comprises an active back termination circuit.
A second aspect of the present invention is A analogue-digital combined amplifier comprising:
wherein the output of said analogue-digital combined amplifier is a combination of the output of said non-linear digital amplifier and said analogue linear amplifier.
Also in this aspect, the linear amplifier can be selected from the group consisting of class A and class A/B amplifiers, and the non-linear amplifier is preferably selected from the group consisting of switching mode amplifiers, clipping amplifiers, class B, G or K amplifiers and pulse width modulation amplifiers.
Another aspect of the present invention is a method for amplifying an input signal, comprising the following steps:
Said combination step can be performed using a hybrid, and the input signal can be generated by a DMT.
The present invention describes a novel line driver, called C-AB driver. It comprises at least an analogue linear amplifier, coupled in parallel with a non-linear line driver and producing only a small part of the output signal power, and can compensate for the errors in the output signal from the non-linear line driver due to power supply variations and clock jitter.
An example of a class C-AB driver according to the present invention can be seen in FIG. 2.
The class C-AB driver 1 comprises a nonlinear amplifier 3, being the independent source, and further comprises an analogue linear amplifier 5 which is controlled to compensate for the non linearity of the non-linear amplifier 3 and thus is dependent.
According to the present invention, the analogue linear amplifier 5 compares the input signal 11 as sent by the DMT 2 and converted digital to analogue by D/A converter 15 with the output signal 13 at the output of the non-linear amplifier 3. The difference between these signals is compensated for by the analogue linear amplifier 5 and the output of both the non-linear amplifier 3 and the analogue linear amplifier 5 are combined by hybrid 9 and sent on line 7.
The non-linear amplifier can be any non-linear amplifier. Examples are clipping amplifiers, switching mode amplifiers, class K, G or B amplifiers, pulse width modulators, . . . . The analogue linear amplifier can be any analogue linear amplifier, such as a class A or class A/B amplifier.
A 3′rd order/4′th order RC or LC filter (Fl) is required to limit the band to 1 Mhz if a switching mode driver is used as the non-linear amplifiers.
It is clear that the set-up of the present invention can be combined with other power-saving techniques, such as active back termination.
In
According to this embodiment, as can be seen in
The distortion due to power supply changes and clock jitter in this embodiment is reduced by a factor 5 to 8 in comparison with the traditional switching mode line driver as in FIG. 1.
An additional advantage with the class C-AB line driver according to the invention is that power supply can be simplified compared to the traditional G-class amplifier. A class G amplifier needs GND (ground), +Vcc, +Vcc/2, −Vcc and −Vcc/2 potentials. The non-linear and linear amplifier of the class C-AB line driver according to the invention only need +Vcc, −Vcc and GND connections. DC-de-coupling capacitors, inserted at the output of the non-linear amplifier are useful to avoid power supply asymmetry effects when driving the line with two non-linear amplifiers.
Number | Date | Country | Kind |
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00403694 | Dec 2000 | EP | regional |
Number | Name | Date | Kind |
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3763437 | Seidel | Oct 1973 | A |
3815040 | Seidel | Jun 1974 | A |
3873936 | Cho | Mar 1975 | A |
5930128 | Dent | Jul 1999 | A |
6075411 | Briffa et al. | Jun 2000 | A |
Number | Date | Country |
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0 901 221 | Mar 1999 | EP |
Number | Date | Country | |
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20020084811 A1 | Jul 2002 | US |