BACKGROUND
Field of the Invention
The field of the invention is data processing, or, more specifically, methods and integrated circuits for yielding and routable circuit co-design using viabars.
Description of Related Art
Rectangular viabars may be used instead of or in addition to vias to connect metal layers of a block of an integrated circuit. The use of viabars can improve chip yield compared to standard square vias. However, using viabars instead of standard square vias results in additional free space usage. As routing must conform to various design rules, the increased use of free space may make routing more difficult or impossible if viabars are overused.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows an example diagram for via placement in integrated circuit designs.
FIG. 1B shows an example diagram for via placement in integrated circuit designs.
FIG. 1C shows an example diagram for via placement in integrated circuit designs.
FIG. 1D shows an example diagram for via placement in integrated circuit designs.
FIG. 2A shows an example diagram for via yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure.
FIG. 2B shows an example diagram for via yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure.
FIG. 2C shows an example diagram for via yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure.
FIG. 3 shows an example flowchart for via yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure.
FIG. 4 shows a block diagram of an example computer for yielding and routable circuit co-design using viabars according to some embodiments of the present disclosure.
FIG. 5 shows a flowchart of an example method for yielding and routable circuit co-design using viabars according to some embodiments of the present disclosure.
FIG. 6 shows a flowchart of another example method for yielding and routable circuit co-design using viabars according to some embodiments of the present disclosure.
FIG. 7 shows a flowchart of another example method for yielding and routable circuit co-design using viabars according to some embodiments of the present disclosure.
SUMMARY
Yielding and routable circuit co-design using viabars, including: creating, in a first metal layer of an integrated circuit design, a first interconnect having a slack portion vertically coinciding with a second interconnect of a second metal layer of the integrated circuit design; creating, in the integrated circuit design, a first via interconnecting the first interconnect and the second interconnect; determining, after block-level signal routing of the integrated circuit design and based on one or more design rules, that the first via can be extended into the slack portion; and extending, based on the determination that the first via can be extended, the first via into a viabar interconnecting the first metal layer and the second metal layer.
DETAILED DESCRIPTION
FIGS. 1A-1C show example diagrams for via placement in integrated circuit designs according to approaches known in the art. Beginning with FIG. 1A, an illustrative diagram of via placement to interconnect metal layers in an integrated circuit is shown. Interconnects 102a and 102b are located in a first metal layer of an integrated circuit. The interconnects 102a,b, as well as other interconnects referred to herein, may include wires or other signal pathways as can be appreciated. Interconnect 104a is located in a second metal layer of the integrated circuit. The second metal layer may be above or below the first metal layer. Additionally, the second metal layer may be separated from the first metal layer by one or more intermediate layers. As shown, interconnects 102a,b are perpendicular to the interconnect 104a.
The first metal layer is interconnected to the second metal layer using vias 106a,b. Here, the via 106a interconnects the interconnect 102a in the first metal layer to the interconnect 104a in the second metal layer while the via 106ab interconnects the interconnect 102ab in the first metal layer to the interconnect 104a in the second metal layer. In some embodiments, the vias 106a,b may be square or substantially square. The vias 106a,b are placed at locations where the interconnect 104a vertically coincides with the interconnect 102a,b, respectively.
Turning now to FIG. 1B, another illustrative diagram of via placement to interconnect metal layers in an integrated circuit is shown. FIG. 1B is similar to FIG. 1A, differing in that FIG. 1B includes interconnects 108a,b located in a third metal layer of the integrated circuit. Though the interconnects 108a,b are shown as having a width less than the interconnects 102a,b or 104a-c, it is understood that this is merely illustrative for the purpose of clarity and that these interconnects, as well as other elements shown in the figures, are not depicted necessarily to scale. Moreover, it is understood that, while some figures may not show an amount of enclosing material around a via or viabar, it is understood that this is also omitted for clarity and that the enclosing material may be present in some embodiments.
FIG. 1B also includes interconnects 104b,c in the second metal layer. The third metal layer is interconnected to the second metal layer using vias 110a,b,c,d. For example, while the first and second metal layer may include cells or components added during a placement stage of design (e.g., before routing), the third metal layer may include wiring (e.g., interconnects 108a,b) added to an integrated circuit chip design during the routing stage. Here, vias 110a,b interconnect the interconnect 104c in the second metal layer to interconnects 108a,b, respectively, in the third metal layer while vias 110c,d interconnect the interconnect 104b in the second metal layer to interconnects 108a,b, respectively, in the third metal layer. As with the via 106a, the vias 110a-d may be substantially square in shape.
Integrated circuits may be required to conform to one or more design rules that describe how components, connections, and the like may be positioned within an integrated circuit. As an example, the one or more design rules may define a minimum distance (e.g., a minimum separation) between vias. The minimum distance may be measured, for example, from the center of one via to another, from the edge of one via to another, and the like. In FIG. 1B, the vias 110a-d satisfy a minimum distance between vias relative to the via 106a.
FIG. 1C sets forth another illustrative diagram of via placement to interconnect metal layers in an integrated circuit is shown. FIG. 1C is similar to FIG. 1A, differing that an interconnect 120 is used instead of an interconnect 102a in the first metal layer. The interconnect 120 differs in shape from the interconnect 102a in that the interconnect 120 includes a slack portion 126. The slack portion 126 is a portion of an interconnect 102a that extends from another portion of the interconnect 102a in a different direction. Here, the slack portion 126 extends orthogonally from another portion of the interconnect 102a, forming a right angle shape. Particularly, the slack portion 126 extends such that it is parallel to the interconnect 104a in the second metal layer. Thus, a greater area of the interconnect 120 vertically coincides with the interconnect 104a compared to the interconnect 102a.
FIGS. 1A and 1B rely on square vias 106a,b and 110a-d to interconnect the various metal layers. In contrast, FIG. 1C uses a viabar 124. Due to the greater amount of vertically coinciding area between the interconnect 120 and the interconnect 104a, a viabar 124 having a greater area than a via 106a may be used. In some embodiments, the viabar 124 may have a width equal or substantially similar to other vias in the integrated circuit, such as square vias including vias 106a,b. The viabar 124 has a length grater than standard square vias (e.g., vias 106a,b). For example, in some embodiments, the viabar 124 may have a length equal or substantially equal to twice the length of a standard square via in the same integrated circuit. In other words, a viabar 124 may have an aspect ratio of 1:2 compared to square vias having an aspect ratio of 1:1. In some embodiments, the viabar 124 may have another length greater than that of a standard square via in the same integrated circuit. The use of viabars instead of standard square vias to interconnect metal layers in an integrated circuit results in a greater yield during chip manufacturing. Viabars also have comparatively smaller resistance, reducing interconnect RC delay.
Though the use of viabars instead of square vias improves chip yield, their increased size may present challenges during routing, as shown in FIG. 1D. For example, assume that, during the cell placement design stage of an integrated circuit, a viabar 124 is placed to interconnect the interconnect 120 of the first metal layer to the interconnect 104a of the second metal layer. Further assume that the integrated circuit of FIG. 1D has more conservative design placement rules compared to FIG. 1B, resulting in a greater minimum distance between vias (or viabars, where applicable). Accordingly, placement of vias 110a-d, added during the routing stage, would be invalid due to the presence of the viabar 124.
To address these shortcomings, FIGS. 2A-2C show illustrative diagrams for yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure. FIG. 2A shows interconnects 202a,b in a first metal layer of an integrated circuit. Interconnect 202a includes a slack portion 204 in parallel with an interconnect 206a in a second metal layer. Assume that interconnects 202a,b and 206a are positioned in a block of an integrated circuit during a placement stage. During this placement stage, vias 208a,b are positioned to interconnect the first metal layer and the second metal layer by interconnecting the interconnect 206a to interconnects 202a,b, respectively. As shown, the via 208b is positioned in the slack portion 204 of the interconnect 202a.
Here, portions of the interconnect 202a on opposing sides of the via 208b vertically coinciding with the interconnect 206a are present. As will be described in further detail below, this provides the ability to later expand the via 208b into a viabar, thereby using more area of the interconnect 202a. For example, the via 208b may be extended toward an end of the slack portion 204 and/or in the opposite direction. Although the via 208b is shown at a particular location, it is understood that this location is merely illustrative and that the via 208b may be placed at any location on the interconnect 202a that is vertically coinciding with the interconnect 206a such that the via 208b may be extended in one or more directions using the slack portion 204 of the interconnect.
FIG. 2B shows another illustrative diagram for yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure. Here, assume that, for a given integrated circuit block, all cells or other components have been placed, including any interconnecting vias. Next, during a routing stage of integrated circuit design, the various components may be routed using wiring or other interconnects. Here, an interconnect 210 in a third metal layer has been added during the routing stage that is to be connected to interconnect 206b in the first metal layer, added during the placement stage, using a via 212. The interconnect 210 and via 212 are added during the routing stage such that they conform to any design rules, including design rules relating to minimum distances between vias. Accordingly, the via 212 is at a distance to the via 208b greater than or equal to this minimum distance.
After routing has been performed, it may then be determined if the via 208b can be extended into a viabar. In FIG. 2B, extending the via 208b into a viabar would result in a viabar having a distance to the via 212 less than the minimum distance defined in the design rules. Accordingly, it is determined that the via 208b should not be extended. Alternatively, in FIG. 2C, assume that no interconnect 210 or via 212 were added during the routing stage. After this routing stage, it may be determined whether the via 208b can be extended into a viabar 214 by determining if such a viabar 214 would violate the design rules. Here, such a viabar 214 would conform to the design rules due to the via 212 not being present. Accordingly, the via 208b is extended into a viabar 214 (e.g., the via 208b is replaced with the viabar 214).
In this example, a first end of the viabar 214 is aligned with a first end of the original via 208b while a second end of the viabar 214 is closer to the end of the slack portion 204 compared to the second end of the original via 208b opposing the first end. In other words, the viabar 214 is created by extending the via 208b in a direction toward an end of the slack portion 204. One skilled in the art will appreciate that, in some embodiments, a viabar 214 may be created by extending the via 208b in the opposing direction, or both directions. Put differently, a via 208b may be extended into a viabar 214 by extending the via 208b in any direction such that the viabar 214 remains in a location where the coupled interconnects 202a and 206a are vertically collocated (e.g., overlapping) and conform to any design rules. For example, the viabar 214 may be extended as far toward the end of the slack portion 204 as desired provided that a space between an edge of the viabar 214 and the end of the slack portion satisfies any design rules defining an amount of encapsulation around vias or viabars, or any other applicable design rules as can be appreciated.
In the examples of FIGS. 2A-2C, during the integrated circuit design process, components (e.g., interconnects, cells, and the like) are placed, including any required vias. Some of these interconnects may include slack portions into which vias may be extended. Next, the routing stage may introduce additional vias, interconnects, and the like. After the routing stage is complete, any via able to be extended using a slack portion of one of their coupled interconnects may be extended, thereby replacing that via with a viabar. The inclusion of slack in the interconnects during the placement stage allows for component placement to be performed while taking into account the shape and space requirements caused by this added slack. Instead of placing viabars during the placement stage, only vias are used. This allows for routing to be performed without any complications caused by viabars being present. Once routing is complete, viabars may be added by extending those vias able to do so while still conforming with the design rules of the integrated circuit. Thus, the integrated circuit design receives the yield benefit of any added viabars while avoiding any routing difficulties that would be caused by their presence during the routing process.
While some slack portions may be used to extend vias into viabars, it may be possible that some of these vias may not be extended due to component placement or routing decisions. Accordingly, in some embodiments, the resulting integrated circuit may include one or more interconnects with slack portions having viabars and one or more other interconnects having slack portions with vias. Thus, these one or more interconnects may include a portion on one or more sides of the via greater than a minimum amount defined by the one or more design rules. Put differently, a given interconnect may have, on one or more sides of a via, a portion vertically coinciding with another interconnect coupled by the via and also exceeding a minimum amount defined by the one or more design rules (e.g., a minimum amount of enclosure).
FIG. 3 sets forth an example flow chart for yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure. Beginning at step 302, during the cell placement stage of integrated circuit design, interconnects in various metal layers are placed, with some of these interconnects including slack portions. Such interconnects are internal to cells (inverters, nands, etc.). Also during this placement stage, vias may be placed in the design in order to couple various pairs of interconnects. Some of these vias, hereinafter referred to as “slack vias” may be placed on a location where the slack portion of a first interconnect to be coupled vertically coincides (e.g., runs parallel) with the second interconnect to be coupled. At step 304, block-level routing is performed in order to couple the various components of an integrated circuit block. For example, wires may be placed in the design and any vias necessary to couple these wires to other interconnects (e.g., in metal layers) may also be placed.
After performing the block-level routing, the process moves to step 306 where it is determined if a slack via is extendable. A slack via is extendable where the slack via may be extended in one or more directions in a slack portion into which the slack via is placed while also conforming to all design rules for the integrated circuit. If the slack via is extendable, the process advances to step 308 where the slack via is extended into a viabar. The slack via is extended into a viabar by replacing the slack via with a viabar that occupies a location having an area greater than and encompassing the area of the slack via. The process then advances to step 310 where it is determined if any slack vias remain (e.g., if any slack vias have not been checked to see if they can be extended into a viabar). If, at step 306, it is determined that a given slack via cannot be extended, the process advances to step 310. If, at step 310, it is determined that any slack vias are remaining, the process returns to step 306. Otherwise, the process ends.
Yielding and routable circuit co-design using viabars in accordance with the present application is generally implemented with computers, that is, with automated computing machinery. For further explanation, therefore, FIG. 4 sets forth a block diagram of computing machinery including an exemplary computer 400 configured for yielding and routable circuit co-design using viabars according to certain embodiments. The computer 400 of FIG. 4 includes at least one computer processor 402 or ‘CPU’ as well as random access memory 404 (‘RAM’) which is connected through a high speed memory bus 406 and bus adapter 408 to processor 402 and to other components of the computer 400.
Stored in RAM 404 is an operating system 410. Operating systems useful in computers configured for yielding and routable circuit co-design using viabars according to certain embodiments include UNIX™. Linux™, Microsoft Windows™, and others as will occur to those of skill in the art. The operating system 410 in the example of FIG. 4 is shown in RAM 404, but many components of such software typically are stored in non-volatile memory also, such as, for example, on data storage 412, such as a disk drive.
The computer 400 of FIG. 4 includes disk drive adapter 416 coupled through expansion bus 418 and bus adapter 408 to processor 402 and other components of the computer 400. Disk drive adapter 416 connects non-volatile data storage to the computer 400 in the form of data storage 412. Disk drive adapters useful in computers configured for yielding and routable circuit co-design using viabars according to certain embodiments include Integrated Drive Electronics (‘IDE’) adapters, Small Computer System Interface (‘SCSI’) adapters, and others as will occur to those of skill in the art. In some embodiments, non-volatile computer memory is implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called ‘EEPROM’ or ‘Flash’ memory), RAM drives, and so on, as will occur to those of skill in the art.
The example computer 400 of FIG. 4 includes one or more input/output (′I/O′) adapters 420. I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices 422 such as keyboards and mice. The example computer 400 of FIG. 4 includes a video adapter 424, which is an example of an I/O adapter specially designed for graphic output to a display device 426 such as a display screen or computer monitor. Video adapter 424 is connected to processor 402 through a high speed video bus 438, bus adapter 408, and the front side bus 430, which is also a high speed bus.
The exemplary computer 400 of FIG. 4 includes a communications adapter 432 for data communications with other computers and for data communications with a data communications network. Such data communications are carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (‘USB’), through data communications networks such as IP data communications networks, and/or in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters useful in computers configured for yielding and routable circuit co-design using viabars according to certain embodiments include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.
For further explanation, FIG. 5 shows a flowchart of an example method for yielding and routable circuit co-design using viabars according to some embodiments of the present disclosure. The method of FIG. 5 may be performed, for example, during the design phase of an integrated circuit block. The method of FIG. 5 includes creating 502, in a first metal layer of an integrated circuit design, a first interconnect having a slack portion vertically coinciding with a second interconnect of a second metal layer of the integrated circuit design. For example, a portion of the first interconnect other than the slack portion may run in a first direction while the second interconnect runs in a second direction perpendicular to the first direction. The slack portion of the first interconnect may therefore also run in a direction parallel to the second interconnect and therefore also run perpendicular to the other portion of the first interconnect. In other words, in some embodiments, the slack portion may be orthogonal to another portion of the first interconnect, thereby forming a right angle in the first interconnect.
The method of FIG. 5 also includes creating 504, in the integrated circuit design, a first via interconnecting the first interconnect and the second interconnect. The first via may include, for example, a square via or a substantially square via. The via may be placed, in the integrated circuit design, at a location where the first interconnect and the second interconnect vertically coincide. In some embodiments, as the slack portion of the first interconnect vertically coincides with the second interconnect, the first via may be at least partially placed in the slack portion of the first interconnect. The first via is positioned such that, after block-level signal routing, the first via may be extended into a viabar provided that such extension would not violate any design rules of the integrated circuit.
The method of FIG. 5 also includes determining 506, after block-level signal routing of the integrated circuit design and based on one or more design rules, that the first via can be extended into the slack portion. As the block-level signal routing may introduce additional vias or other components to the integrated circuit design, these additional vias or components may affect whether the first via can be extended into the slack portion. Here, the first via can be extended into the slack portion as the extended first via (e.g., a viabar) will not violate any design rules.
The method of FIG. 5 also includes extending 508, based on the determination that the first via can be extended, the first via into a viabar interconnecting the first metal layer and the second metal layer. Extending 508 the first via causes the first via to be replaced in the integrated circuit design with a viabar. In some embodiments, the viabar has a width equal or substantially equal to the width of the first via. The viabar has a length greater than the length of the first via. For example, in some embodiments, the viabar has a length twice the length of the first via. In some embodiments, the viabar has a length greater than twice the length of the first via. The viabar is positioned in a location where the first interconnect and the second interconnect vertically coincide, including the slack portion of the first interconnect. In some embodiments, extending the first via into a viabar includes extending the first via in one or more directions. The viabar, after placement, satisfies the one or more design rules for the integrated circuit.
For further explanation, FIG. 6 sets forth a flowchart of an example method of yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure. The method of FIG. 6 is similar to FIG. 5 in that the method of FIG. 6 also includes: creating 502, in a first metal layer of an integrated circuit design, a first interconnect having a slack portion vertically coinciding with a second interconnect of a second metal layer of the integrated circuit design; creating 504, in the integrated circuit design, a first via interconnecting the first interconnect and the second interconnect; determining 506, after block-level signal routing of the integrated circuit design and based on one or more design rules, that the first via can be extended into the slack portion; and extending 508, based on the determination that the first via can be extended, the first via into a viabar interconnecting the first metal layer and the second metal layer.
The method of FIG. 6 differs from FIG. 5 in that the method of FIG. 6 also includes determining 602, after block-level signal routing of the integrated circuit design and based on the one or more design rules, that a second via interconnecting a third interconnect and another interconnect cannot be extended into another slack portion of the third interconnect. The other interconnect may include the first interconnect, the second interconnect, or another interconnect as can be appreciated. This second via is placed at a location where the third interconnect and the other interconnect vertically coincide such that the second via may potentially be extended using the slack portion of the third interconnect provided all design rules are satisfied. After placement of all components during block-level signal routing, it is determined that extending this second via into another viabar would violate one or more design rules. Accordingly, the method of FIG. 6 also includes maintaining 604 the second via instead of extending the second via. In other words, the second via remains in the integrated circuit design instead of being replaced by another viabar.
For further explanation, FIG. 7 sets forth a flowchart of an example method of yielding and routable circuit co-design using viabars in accordance with some embodiments of the present disclosure. The method of FIG. 7 is similar to FIG. 5 in that the method of FIG. 7 also includes: creating 502, in a first metal layer of an integrated circuit design, a first interconnect having a slack portion vertically coinciding with a second interconnect of a second metal layer of the integrated circuit design; creating 504, in the integrated circuit design, a first via interconnecting the first interconnect and the second interconnect; determining 506, after block-level signal routing of the integrated circuit design and based on one or more design rules, that the first via can be extended into the slack portion; and extending 508, based on the determination that the first via can be extended, the first via into a viabar interconnecting the first metal layer and the second metal layer.
The method of FIG. 7 differs from FIG. 5 in that the method of FIG. 7 also includes manufacturing 702 an integrated circuit based on the integrated circuit design. The manufactured integrated circuit includes components placed and connections established according to the integrated circuit design. The integrated circuit design, and therefore the integrated circuit, satisfies all design rules for the integrated circuit. In some embodiments, the resulting integrated circuit may include one or more interconnects with slack portions having viabars and one or more other interconnects having slack portions with vias. Thus, these one or more interconnects may include a portion on one or more sides of the via greater than a minimum amount defined by the one or more design rules. Put differently, a given interconnect may have, on one or more sides of a via, a portion vertically coinciding with another interconnect coupled by the via and also exceeding a minimum amount defined by the one or more design rules (e.g., a minimum amount of enclosure.
In view of the explanations set forth above, readers will recognize that the benefits of yielding and routable circuit co-design using viabars according to embodiments of the present invention include improved performance of a computing system by allowing for improved chip yield by using viabars while allowing for block-level routing to be performed without any constraints introduced by the presence of viabars prior to routing.
Exemplary embodiments of the present invention are described largely in the context of a fully functional computer system for yielding and routable circuit co-design using viabars. Readers of skill in the art will recognize, however, that the present invention also may be embodied in a computer program product disposed upon computer readable storage media for use with any suitable data processing system. Such computer readable storage media may be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the invention as embodied in a computer program product. Persons skilled in the art will recognize also that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present invention.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.
Patent Application
20250005252
