Zapping Circuit

Abstract

In a zapping circuit of the present invention, resistances each formed of a polysilicon film or a tungsten silicon film are used as zapping elements. As driver elements for partially or completely fusing the resistances, low breakdown voltage MOS transistors are used. Using the MOS transistors makes it possible to reduce a region in which to form the driver elements for zapping, and to thus reduce an IC chip area.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a switching circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a current regulation circuit according to the embodiment of the present invention.

FIG. 3A is a circuit diagram illustrating a sense circuit using NPN transistors, and FIG. 3B is a circuit diagram illustrating a sense circuit using N-channel MOS transistors according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a current regulation circuit according to a conventional embodiment.

Claims

1. A zapping circuit comprising: resistances connected to a power supply circuit; andtransistors which supply currents to the resistances, whereinthe transistors have a current capacity to partially or completely fuse the resistances.

2. The zapping circuit as recited in claim 1, wherein the transistors are MOS transistors.

3. The zapping circuit as recited in claim 2, further comprising a control circuit which controls operations of the MOS transistors,wherein the MOS transistors are operated based on control signals from the control circuit.

4. The zapping circuit as recited in claim 3, wherein the plurality of resistances and the plurality of MOS transistors are respectively paired with each other, and connected in parallel to the power supply circuit, andthe MOS transistors are selectively turned on based on the control signals from the control circuit.

5. The zapping circuit as recited in claim 4, further comprising a sense circuit which detects changes in resistance values respectively of the resistances.

6. The zapping circuit as recited in any one of claims 1 and 2, wherein the resistances are formed of any one of a polysilicon film and a tungsten silicon film.

7. The zapping circuit as recited in any one of claims 1 and 2, wherein the resistances have resistance values of 10Ω to 1 kΩ.