ADEIA SEMICONDUCTOR SOLUTIONS LLC

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SAN JOSE, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Nanosheet channel-to-source and drain isolation
- Patent number 12,166,110
- Issue date Dec 10, 2024
- Adeia Semiconductor Solutions LLC
- Marc A. Bergendahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming nanosheet transistor using sacrificial spacer and inner spa...
- Patent number 12,154,971
- Issue date Nov 26, 2024
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of a vertical fin field effect transistor with reduced...
- Patent number 12,136,573
- Issue date Nov 5, 2024
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Punch through stopper in bulk finFET device
- Patent number 12,119,393
- Issue date Oct 15, 2024
- Adeia Semiconductor Solutions LLC
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a porous dielectric layer, and metho...
- Patent number 11,955,424
- Issue date Apr 9, 2024
- Adeia Semiconductor Solutions LLC
- Benjamin David Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanosheet transistor
- Patent number 11,901,438
- Issue date Feb 13, 2024
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Forming a sacrificial liner for dual channel devices
- Patent number 11,894,462
- Issue date Feb 6, 2024
- Adeia Semiconductor Solutions LLC
- Huiming Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM design to facilitate single fin cut in double sidewall image t...
- Patent number RE49794
- Issue date Jan 9, 2024
- Adeia Semiconductor Solutions LLC
- Mary E. Weybright
Information Patent Grant
Fabrication of a vertical fin field effect transistor with reduced...
- Patent number 11,784,095
- Issue date Oct 10, 2023
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NANOSHEET TRANSISTOR
- Publication number 20240413224
- Publication date Dec 12, 2024
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...
- Publication number 20240413076
- Publication date Dec 12, 2024
- Adeia Semiconductor Solutions LLC
- Benjamin David Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE
- Publication number 20240387264
- Publication date Nov 21, 2024
- Adeia Semiconductor Solutions LLC
- Daniel C. Edelstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
- Publication number 20240363755
- Publication date Oct 31, 2024
- Adeia Semiconductor Solutions LLC
- Huiming Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20240347383
- Publication date Oct 17, 2024
- Adeia Semiconductor Solutions LLC
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID-CHANNEL NANO-SHEET FETS
- Publication number 20240274475
- Publication date Aug 15, 2024
- Adeia Semiconductor Solutions LLC
- Zhenxing Bi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RAN...
- Publication number 20240258113
- Publication date Aug 1, 2024
- Adeia Semiconductor Solutions LLC
- Fee Li Lie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED...
- Publication number 20240249980
- Publication date Jul 25, 2024
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE
- Publication number 20240203930
- Publication date Jun 20, 2024
- Adeia Semiconductor Solutions LLC
- Hiroaki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING COPPER INTERCONNECT STRUCTURE WITH MANGANESE BARR...
- Publication number 20240006237
- Publication date Jan 4, 2024
- Adeia Semiconductor Solutions LLC
- Daniel C. Edelstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF FINS USING VARIABLE SPACERS
- Publication number 20230360923
- Publication date Nov 9, 2023
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...
- Publication number 20230361023
- Publication date Nov 9, 2023
- Adeia Semiconductor Solutions LLC
- Benjamin David Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED...
- Publication number 20230282522
- Publication date Sep 7, 2023
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Organization

Patents Grantslast 30 patents

Nanosheet channel-to-source and drain isolation

Forming nanosheet transistor using sacrificial spacer and inner spa...

Fabrication of a vertical fin field effect transistor with reduced...

Punch through stopper in bulk finFET device

Semiconductor device including a porous dielectric layer, and metho...

Nanosheet transistor

Forming a sacrificial liner for dual channel devices

SRAM design to facilitate single fin cut in double sidewall image t...

Fabrication of a vertical fin field effect transistor with reduced...

Patents Applicationslast 30 patents

NANOSHEET TRANSISTOR

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...

ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

HYBRID-CHANNEL NANO-SHEET FETS

TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RAN...

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

METHOD OF FORMING COPPER INTERCONNECT STRUCTURE WITH MANGANESE BARR...

FABRICATION OF FINS USING VARIABLE SPACERS

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED...

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