BiTMICRO LLC

Organization

Reston, VA, US

Organizations

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Patents Grantslast 30 patents

Information Patent Grant
Multilevel memory bus system
- Patent number 10,877,907
- Issue date Dec 29, 2020
- BiTMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-mapped DMA transfer with dependency table configured to monitor...
- Patent number 10,872,050
- Issue date Dec 22, 2020
- BiTMICRO LLC
- Cyrill C. Ponce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimensional computer storage system
- Patent number 10,552,050
- Issue date Feb 4, 2020
- BiTMICRO LLC
- Marlon B. Verdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive power cycle sequences for data recovery
- Patent number 10,540,242
- Issue date Jan 21, 2020
- BiTMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write buffering
- Patent number 10,445,239
- Issue date Oct 15, 2019
- BiTMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-mapped DMA transfer with dependency table configured to monitor...
- Patent number 10,372,643
- Issue date Aug 6, 2019
- BiTMICRO LLC
- Cyrill C. Ponce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-leveled cache management in a hybrid storage system
- Patent number 10,210,084
- Issue date Feb 19, 2019
- BiTMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive power cycle sequences for data recovery
- Patent number 10,180,887
- Issue date Jan 15, 2019
- BiTMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solid state drive with improved enclosure assembly
- Patent number 10,149,399
- Issue date Dec 4, 2018
- BiTMICRO LLC
- Rogelio Gazmen Mangay-Ayam
- G11 - INFORMATION STORAGE
Information Patent Grant
Multilevel memory bus system
- Patent number 10,133,686
- Issue date Nov 20, 2018
- BiTMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory transaction with reduced latency
- Patent number 10,120,586
- Issue date Nov 6, 2018
- BITMICRO, LLC
- Rey H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic storage device
- Patent number 10,082,966
- Issue date Sep 25, 2018
- BiTMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-mapped DMA transfer with dependency table configured to monitor...
- Patent number 10,042,799
- Issue date Aug 7, 2018
- BITMICRO, LLC
- Cyrill C. Ponce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage system with distributed ECC capability
- Patent number 9,996,419
- Issue date Jun 12, 2018
- BiTMICRO LLC
- Rey H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-mapped DMA and IOC transfer with dependency table comprising pl...
- Patent number 9,934,160
- Issue date Apr 3, 2018
- BiTMICRO LLC
- Cyrill C. Ponce
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WRITE BUFFERING
- Publication number 20200151098
- Publication date May 14, 2020
- BITMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE POWER CYCLE SEQUENCES FOR DATA RECOVERY
- Publication number 20190220373
- Publication date Jul 18, 2019
- BITMICRO LLC
- Rolando H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL MEMORY BUS SYSTEM
- Publication number 20190087363
- Publication date Mar 21, 2019
- BITMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING

BiTMICRO LLC

Organization

Patents Grantslast 30 patents

Multilevel memory bus system

Bit-mapped DMA transfer with dependency table configured to monitor...

Multi-dimensional computer storage system

Adaptive power cycle sequences for data recovery

Write buffering

Bit-mapped DMA transfer with dependency table configured to monitor...

Multi-leveled cache management in a hybrid storage system

Adaptive power cycle sequences for data recovery

Solid state drive with improved enclosure assembly

Multilevel memory bus system

Memory transaction with reduced latency

Electronic storage device

Bit-mapped DMA transfer with dependency table configured to monitor...

Storage system with distributed ECC capability

Bit-mapped DMA and IOC transfer with dependency table comprising pl...

Patents Applicationslast 30 patents

WRITE BUFFERING

ADAPTIVE POWER CYCLE SEQUENCES FOR DATA RECOVERY

MULTILEVEL MEMORY BUS SYSTEM

Trademarklast 30 trademarks