D3 Semiconductor LLC

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Addison, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Super junction MOS bipolar transistor having drain gaps
- Patent number 10,580,884
- Issue date Mar 3, 2020
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Termination region architecture for vertical power transistors
- Patent number 10,134,890
- Issue date Nov 20, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface devices within a vertical power device
- Patent number 10,074,735
- Issue date Sep 11, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for precision enhancement of vertica...
- Patent number 9,997,455
- Issue date Jun 12, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for improved packing of vertical fie...
- Patent number 9,865,727
- Issue date Jan 9, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source-gate region architecture in a vertical power semiconductor d...
- Patent number 9,837,358
- Issue date Dec 5, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Termination region architecture for vertical power transistors
- Patent number 9,806,186
- Issue date Oct 31, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface devices within a vertical power device
- Patent number 9,755,058
- Issue date Sep 5, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for precision enhancement of vertica...
- Patent number 9,589,889
- Issue date Mar 7, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for improved packing of vertical fie...
- Patent number 9,496,386
- Issue date Nov 15, 2016
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for improved packing of vertical fie...
- Patent number 9,117,899
- Issue date Aug 25, 2015
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device architecture and method for precision enhancement of vertica...
- Patent number 9,117,709
- Issue date Aug 25, 2015
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUPER JUNCTION MOS BIPOLAR TRANSISTOR AND PROCESS OF MANUFACTURE
- Publication number 20200203511
- Publication date Jun 25, 2020
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE
- Publication number 20200026517
- Publication date Jan 23, 2020
- D3 Semiconductor, LLC
- Thomas E. Harrington
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Termination Region Architecture for Vertical Power Transistors
- Publication number 20180277673
- Publication date Sep 27, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPER JUNCTION MOS BIPOLAR TRANSISTOR AND PROCESS OF MANUFACTURE
- Publication number 20180261691
- Publication date Sep 13, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Source-Gate Region Architecture in a Vertical Power Semiconductor D...
- Publication number 20180174968
- Publication date Jun 21, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE
- Publication number 20180012981
- Publication date Jan 11, 2018
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...
- Publication number 20170179024
- Publication date Jun 22, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Termination Region Architecture for Vertical Power Transistors
- Publication number 20170098705
- Publication date Apr 6, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Source-Gate Region Architecture in a Vertical Power Semiconductor D...
- Publication number 20170098609
- Publication date Apr 6, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...
- Publication number 20170062606
- Publication date Mar 2, 2017
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE
- Publication number 20160254373
- Publication date Sep 1, 2016
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...
- Publication number 20150340318
- Publication date Nov 26, 2015
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...
- Publication number 20150340454
- Publication date Nov 26, 2015
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR TEMPERATURE COMPENSATION OF VERT...
- Publication number 20140264343
- Publication date Sep 18, 2014
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...
- Publication number 20140145245
- Publication date May 29, 2014
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...
- Publication number 20140145240
- Publication date May 29, 2014
- D3 Semiconductor LLC
- Thomas E. Harrington
- H01 - BASIC ELECTRIC ELEMENTS

Trademarklast 30 trademarks

Information Trademark
86799148 - 35POWER
- Serial number 86799148
- Filing date Oct 26, 2015
- D3 Semiconductor, LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
86697942 - OCTOFET
- Serial number 86697942
- Filing date Jul 20, 2015
- D3 Semiconductor, LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
86405815 - D
- Serial number 86405815
- Registration number 4735054
- Filing date Sep 25, 2014
- D3 Semiconductor LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
85891586 - +FET
- Serial number 85891586
- Registration number 5110053
- Filing date Apr 1, 2013
- D3 Semiconductor LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
85627380 - D3 SEMICONDUCTOR
- Serial number 85627380
- Registration number 4748287
- Filing date May 16, 2012
- D3 Semiconductor, LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
85583375 - OCTOFET
- Serial number 85583375
- Filing date Mar 29, 2012
- D3 Semiconductor, LLC
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

D3 Semiconductor LLC

Organization

Patents Grantslast 30 patents

Super junction MOS bipolar transistor having drain gaps

Termination region architecture for vertical power transistors

Surface devices within a vertical power device

Device architecture and method for precision enhancement of vertica...

Device architecture and method for improved packing of vertical fie...

Source-gate region architecture in a vertical power semiconductor d...

Termination region architecture for vertical power transistors

Surface devices within a vertical power device

Device architecture and method for precision enhancement of vertica...

Device architecture and method for improved packing of vertical fie...

Device architecture and method for improved packing of vertical fie...

Device architecture and method for precision enhancement of vertica...

Patents Applicationslast 30 patents

SUPER JUNCTION MOS BIPOLAR TRANSISTOR AND PROCESS OF MANUFACTURE

SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE

Termination Region Architecture for Vertical Power Transistors

SUPER JUNCTION MOS BIPOLAR TRANSISTOR AND PROCESS OF MANUFACTURE

Source-Gate Region Architecture in a Vertical Power Semiconductor D...

SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE

DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...

Termination Region Architecture for Vertical Power Transistors

Source-Gate Region Architecture in a Vertical Power Semiconductor D...

DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...

SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE

DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...

DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...

DEVICE ARCHITECTURE AND METHOD FOR TEMPERATURE COMPENSATION OF VERT...

DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIE...

DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICA...

Trademarklast 30 trademarks

86799148 - 35POWER

86697942 - OCTOFET

86405815 - D

85891586 - +FET

85627380 - D3 SEMICONDUCTOR

85583375 - OCTOFET