HGST B.V

Organization

LUNA ARENA, NL

Organizations

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Intelligent redundant array of independent disks with high performa...
- Patent number 10,474,572
- Issue date Nov 12, 2019
- HGST, INC.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Persistent file handle object container memory expiry
- Patent number 10,095,700
- Issue date Oct 9, 2018
- HGST, INC.
- Senthilkumar Narayanasamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory shrinker for metadata optimization
- Patent number 10,078,642
- Issue date Sep 18, 2018
- HGST, INC.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable and persistent L2 adaptive replacement cache
- Patent number 10,061,775
- Issue date Aug 28, 2018
- HGST, INC.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solid state devices having fine pitch structures
- Patent number 10,008,542
- Issue date Jun 26, 2018
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
4F2 SCR memory device
- Patent number 9,871,043
- Issue date Jan 16, 2018
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition method for planar surfaces
- Patent number 9,837,269
- Issue date Dec 5, 2017
- HGST, INC.
- Mac D. Apodaca
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming PCM and RRAM 3-D memory cells
- Patent number 9,837,472
- Issue date Dec 5, 2017
- HGST, INC.
- Daniel Robert Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incremental error detection and correction for memories
- Patent number 9,819,365
- Issue date Nov 14, 2017
- HGST, INC.
- Daniel R. Shepard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Embedded non-volatile memory
- Patent number 9,812,503
- Issue date Nov 7, 2017
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NMOS regulated voltage reference
- Patent number 9,753,481
- Issue date Sep 5, 2017
- HGST, INC.
- R. Jacob Baker
- G05 - CONTROLLING REGULATING
Information Patent Grant
3-D planes memory device
- Patent number 9,679,946
- Issue date Jun 13, 2017
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming PCM and RRAM 3-D memory cells
- Patent number 9,570,516
- Issue date Feb 14, 2017
- HGST, INC.
- Daniel Robert Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple bit per cell dual-alloy GST memory elements
- Patent number 9,490,426
- Issue date Nov 8, 2016
- HGST, INC.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned memory cell contact
- Patent number 9,450,182
- Issue date Sep 20, 2016
- HGST, INC.
- Mac D. Apodaca
- G11 - INFORMATION STORAGE
Information Patent Grant
Solid state devices having fine pitch structures
- Patent number 9,437,657
- Issue date Sep 6, 2016
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded non-volatile memory
- Patent number 9,431,460
- Issue date Aug 30, 2016
- HGST, INC.
- Daniel R. Shepard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling coupling in large cross-point memory arrays
- Patent number 9,349,447
- Issue date May 24, 2016
- HGST, INC.
- Thomas Trent
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating a resistive array
- Patent number 9,349,448
- Issue date May 24, 2016
- HGST, INC.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical switch three-dimensional memory array
- Patent number 9,305,624
- Issue date Apr 5, 2016
- HGST, INC.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE
Information Patent Grant
Bipolar-MOS memory circuit
- Patent number 9,270,269
- Issue date Feb 23, 2016
- HGST, INC.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple sector parallel access memory array with error correction
- Patent number 9,195,540
- Issue date Nov 24, 2015
- HGST, INC.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Intelligent Redundant Array of Independent Disks
- Publication number 20190056865
- Publication date Feb 21, 2019
- HGST, Inc.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Predictable Client Latency Via Background File System Operations
- Publication number 20190056871
- Publication date Feb 21, 2019
- HGST, Inc.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Predictable Allocation Latency in Fragmented Log Structured File Sy...
- Publication number 20190057121
- Publication date Feb 21, 2019
- HGST, Inc.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intelligent Redundant Array Of Independent Disks With High Performa...
- Publication number 20190057024
- Publication date Feb 21, 2019
- HGST, Inc.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intelligent Redundant Array Of Independent Disks With Resilvering B...
- Publication number 20190057004
- Publication date Feb 21, 2019
- HGST, Inc.
- Shailendra Tripathi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES
- Publication number 20180069573
- Publication date Mar 8, 2018
- HGST, Inc.
- Daniel R. SHEPARD
- G11 - INFORMATION STORAGE
Information Patent Application
3-D PLANES MEMORY DEVICE
- Publication number 20170271407
- Publication date Sep 21, 2017
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS
- Publication number 20170133435
- Publication date May 11, 2017
- HGST, Inc.
- Daniel Robert SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
4F2 SCR MEMORY DEVICE
- Publication number 20170062432
- Publication date Mar 2, 2017
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED MEMORY CELL CONTACT
- Publication number 20160372659
- Publication date Dec 22, 2016
- HGST, Inc.
- Mac D. APODACA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED NON-VOLATILE MEMORY
- Publication number 20160351627
- Publication date Dec 1, 2016
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BOUNDARY SCAN TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS IN...
- Publication number 20160306011
- Publication date Oct 20, 2016
- HGST, Inc.
- Gobinathan Athimolom
- G01 - MEASURING TESTING
Information Patent Application
SELF-TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS INTERFACE
- Publication number 20160306006
- Publication date Oct 20, 2016
- HGST, Inc.
- Gurjit Chadha
- G01 - MEASURING TESTING
Information Patent Application
SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES
- Publication number 20160293667
- Publication date Oct 6, 2016
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS
- Publication number 20160218147
- Publication date Jul 28, 2016
- HGST, Inc.
- Daniel Robert SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEPOSITION METHOD FOR PLANAR SURFACES
- Publication number 20160155636
- Publication date Jun 2, 2016
- HGST, Inc.
- Mac D. APODACA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NMOS REGULATED VOLTAGE REFERENCE
- Publication number 20160124456
- Publication date May 5, 2016
- HGST, Inc.
- R. Jacob Baker
- G05 - CONTROLLING REGULATING
Information Patent Application
3-D PLANES MEMORY DEVICE
- Publication number 20160056206
- Publication date Feb 25, 2016
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED MEMORY CELL CONTACT
- Publication number 20160020391
- Publication date Jan 21, 2016
- HGST, Inc.
- Mac D. APODACA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED NON-VOLATILE MEMORY
- Publication number 20160020253
- Publication date Jan 21, 2016
- HGST, Inc.
- Daniel R. SHEPARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES
- Publication number 20160019112
- Publication date Jan 21, 2016
- HGST, Inc.
- Daniel R. Shepard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE BIT PER CELL DUAL-ALLOY GST MEMORY ELEMENTS
- Publication number 20160012889
- Publication date Jan 14, 2016
- HGST, Inc.
- Daniel R. Shepard
- G11 - INFORMATION STORAGE
Information Patent Application
VARIABLE SELECTIVITY SILICON GROWTH PROCESS
- Publication number 20150372226
- Publication date Dec 24, 2015
- HGST, Inc.
- Mac D. APODACA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACKNOWLEDGEMENT-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE
- Publication number 20150081955
- Publication date Mar 19, 2015
- HGST
- Dejan VUCINIC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOORBELL-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE
- Publication number 20150081956
- Publication date Mar 19, 2015
- HGST
- Dejan VUCINIC
- G06 - COMPUTING CALCULATING COUNTING

Organization

Patents Grantslast 30 patents

Intelligent redundant array of independent disks with high performa...

Persistent file handle object container memory expiry

Dynamic memory shrinker for metadata optimization

Scalable and persistent L2 adaptive replacement cache

Solid state devices having fine pitch structures

4F2 SCR memory device

Deposition method for planar surfaces

Method for forming PCM and RRAM 3-D memory cells

Incremental error detection and correction for memories

Embedded non-volatile memory

NMOS regulated voltage reference

3-D planes memory device

Method for forming PCM and RRAM 3-D memory cells

Multiple bit per cell dual-alloy GST memory elements

Self-aligned memory cell contact

Solid state devices having fine pitch structures

Embedded non-volatile memory

Controlling coupling in large cross-point memory arrays

Operating a resistive array

Vertical switch three-dimensional memory array

Bipolar-MOS memory circuit

Multiple sector parallel access memory array with error correction

Patents Applicationslast 30 patents

Intelligent Redundant Array of Independent Disks

Predictable Client Latency Via Background File System Operations

Predictable Allocation Latency in Fragmented Log Structured File Sy...

Intelligent Redundant Array Of Independent Disks With High Performa...

Intelligent Redundant Array Of Independent Disks With Resilvering B...

INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES

3-D PLANES MEMORY DEVICE

METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS

4F2 SCR MEMORY DEVICE

SELF-ALIGNED MEMORY CELL CONTACT

EMBEDDED NON-VOLATILE MEMORY

BOUNDARY SCAN TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS IN...

SELF-TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS INTERFACE

SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES

METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS

DEPOSITION METHOD FOR PLANAR SURFACES

NMOS REGULATED VOLTAGE REFERENCE

3-D PLANES MEMORY DEVICE

SELF-ALIGNED MEMORY CELL CONTACT

EMBEDDED NON-VOLATILE MEMORY

INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES

MULTIPLE BIT PER CELL DUAL-ALLOY GST MEMORY ELEMENTS

VARIABLE SELECTIVITY SILICON GROWTH PROCESS

ACKNOWLEDGEMENT-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE

DOORBELL-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE

Trademarklast 30 trademarks