INAPAC TECHNOLOGY, INC

Organization

SAN JOSE, CA, US

Business Address
2770 HUFF DRIVE PLEASONTON CA 94588
State Location
CA
State of Incorporation

Organizations

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Patents Grantslast 30 patents

Information Patent Grant
Shared memory bus architecture for system with processor and memory...
- Patent number 7,466,160
- Issue date Dec 16, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Memory accessing circuit system
- Patent number 7,466,603
- Issue date Dec 16, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit testing module including address generator
- Patent number 7,446,551
- Issue date Nov 4, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture and method for testing of an integrated circuit device
- Patent number 7,444,575
- Issue date Oct 28, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Electronic device having an interface supported testing mode
- Patent number 7,443,188
- Issue date Oct 28, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Component testing and recovery
- Patent number 7,404,117
- Issue date Jul 22, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit testing module including data compression
- Patent number 7,370,256
- Issue date May 6, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit testing module including data generator
- Patent number 7,365,557
- Issue date Apr 29, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Internally generating patterns for testing in an integrated circuit...
- Patent number 7,313,740
- Issue date Dec 25, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit testing module including command driver
- Patent number 7,310,000
- Issue date Dec 18, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device having an interface supported testing mode
- Patent number 7,309,999
- Issue date Dec 18, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit test array including test module
- Patent number 7,307,442
- Issue date Dec 11, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay lock loop delay adjusting method and apparatus
- Patent number 7,269,524
- Issue date Sep 11, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit testing module
- Patent number 7,265,570
- Issue date Sep 4, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Bonding pads for testing of a semiconductor device
- Patent number 7,259,582
- Issue date Aug 21, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Shared bond pad for testing a memory within a packaged semiconducto...
- Patent number 7,245,141
- Issue date Jul 17, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple power levels for a chip within a multi-chip semiconductor...
- Patent number 7,240,254
- Issue date Jul 3, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
System and methods for a high-speed dynamic data bus
- Patent number 7,157,940
- Issue date Jan 2, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip testing within a multi-chip semiconductor package
- Patent number 7,139,945
- Issue date Nov 21, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Monitoring signals between two integrated circuit devices within a...
- Patent number 7,133,798
- Issue date Nov 7, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Testing of integrated circuit devices
- Patent number 7,103,815
- Issue date Sep 5, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout and use of bond pads and probe pads for testing of integrate...
- Patent number 7,061,263
- Issue date Jun 13, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Set up for a first integrated circuit chip to allow for testing of...
- Patent number 7,006,940
- Issue date Feb 28, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed segmented data bus architecture
- Patent number 6,996,652
- Issue date Feb 7, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bonding pads for testing of a semiconductor device
- Patent number 6,882,171
- Issue date Apr 19, 2005
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Entering test mode and accessing of a packaged semiconductor device
- Patent number 6,812,726
- Issue date Nov 2, 2004
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Testing of integrated circuit devices
- Patent number 6,754,866
- Issue date Jun 22, 2004
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip testing within a multi-chip semiconductor package
- Patent number 6,732,304
- Issue date May 4, 2004
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for determining the operating point of a semicon...
- Patent number 6,693,449
- Issue date Feb 17, 2004
- Inapac Technology, Inc.
- Douglas W. Gorgen
- G01 - MEASURING TESTING
Information Patent Grant
Configurable addressing for multiple chips in a package
- Patent number 6,657,914
- Issue date Dec 2, 2003
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory accessing circuit system
- Publication number 20080089139
- Publication date Apr 17, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
Electronic device having an interface supported testing mode
- Publication number 20080061811
- Publication date Mar 13, 2008
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Isolating electric paths in semiconductor device packages
- Publication number 20070241443
- Publication date Oct 18, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit testing module including data compression
- Publication number 20070168808
- Publication date Jul 19, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Component testing and recovery
- Publication number 20070094555
- Publication date Apr 26, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
Shared memory bus architecture for system with processor and memory...
- Publication number 20070013402
- Publication date Jan 18, 2007
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Electronic device having an interface supported testing mode
- Publication number 20060279308
- Publication date Dec 14, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit test array including test module
- Publication number 20060253266
- Publication date Nov 9, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Shared bond pad for testing a memory within a packaged semiconducto...
- Publication number 20060152241
- Publication date Jul 13, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit testing module
- Publication number 20060150046
- Publication date Jul 6, 2006
- Inapac Technology, Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING

Trademarklast 30 trademarks

Information Trademark
78510304 - VIBE
- Serial number 78510304
- Registration number 3412693
- Filing date Nov 2, 2004
- Inapac Technology, Inc.
- 42 - Scientific and technological services and research and design relating thereto
Information Trademark
76035608 - I
- Serial number 76035608
- Registration number 2660191
- Filing date Apr 26, 2000
- Inapac Technology, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76034771 - INAPAC
- Serial number 76034771
- Registration number 2660188
- Filing date Apr 24, 2000
- Inapac Technology, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

INAPAC TECHNOLOGY, INC

Organization

Business Address

State Location

State of Incorporation

Patents Grantslast 30 patents

Shared memory bus architecture for system with processor and memory...

Memory accessing circuit system

Integrated circuit testing module including address generator

Architecture and method for testing of an integrated circuit device

Electronic device having an interface supported testing mode

Component testing and recovery

Integrated circuit testing module including data compression

Integrated circuit testing module including data generator

Internally generating patterns for testing in an integrated circuit...

Integrated circuit testing module including command driver

Electronic device having an interface supported testing mode

Integrated circuit test array including test module

Delay lock loop delay adjusting method and apparatus

Integrated circuit testing module

Bonding pads for testing of a semiconductor device

Shared bond pad for testing a memory within a packaged semiconducto...

Multiple power levels for a chip within a multi-chip semiconductor...

System and methods for a high-speed dynamic data bus

Chip testing within a multi-chip semiconductor package

Monitoring signals between two integrated circuit devices within a...

Testing of integrated circuit devices

Layout and use of bond pads and probe pads for testing of integrate...

Set up for a first integrated circuit chip to allow for testing of...

High-speed segmented data bus architecture

Bonding pads for testing of a semiconductor device

Entering test mode and accessing of a packaged semiconductor device

Testing of integrated circuit devices

Chip testing within a multi-chip semiconductor package

Circuit and method for determining the operating point of a semicon...

Configurable addressing for multiple chips in a package

Patents Applicationslast 30 patents

Memory accessing circuit system

Electronic device having an interface supported testing mode

Isolating electric paths in semiconductor device packages

Integrated circuit testing module including data compression

Component testing and recovery

Shared memory bus architecture for system with processor and memory...

Electronic device having an interface supported testing mode

Integrated circuit test array including test module

Shared bond pad for testing a memory within a packaged semiconducto...

Integrated circuit testing module

Trademarklast 30 trademarks

78510304 - VIBE

76035608 - I

76034771 - INAPAC