JASPER DESIGN AUTOMATION AB

Organization

GOTEBORG, SE

Business Address
100 VIEW STREET SUITE 100 MOUNTAIN VIEW CA 94041 6509660229
Mailing Address
100 VIEW STREET SUITE 100 MOUNTAIN VIEW CA 94041
State Location
CA
State of Incorporation

Organizations

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Functional property ranking
- Patent number 9,460,252
- Issue date Oct 4, 2016
- Jasper Design Automation, Inc.
- Asa Ben-Tzur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Security data path verification
- Patent number 9,449,196
- Issue date Sep 20, 2016
- Jasper Design Automation, Inc.
- Victor Markus Purri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware retention flop list analysis and modification
- Patent number 9,104,824
- Issue date Aug 11, 2015
- Jasper Design Automation, Inc.
- Lawrence Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manipulation of traces for debugging a circuit design
- Patent number 9,081,927
- Issue date Jul 14, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manipulation of traces for debugging behaviors of a circuit design
- Patent number 8,990,745
- Issue date Mar 24, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visualization constraints for circuit designs
- Patent number 8,984,461
- Issue date Mar 17, 2015
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Veryifing low power functionality through RTL transformation
- Patent number 8,954,904
- Issue date Feb 10, 2015
- Jasper Design Automation, Inc.
- Lawrence Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraining traces in formal verification
- Patent number 8,863,049
- Issue date Oct 14, 2014
- Jasper Design Automation, Inc.
- Lars Lundgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indexing behaviors and recipes of a circuit design
- Patent number 8,831,925
- Issue date Sep 9, 2014
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics for circuit design properties
- Patent number 8,826,201
- Issue date Sep 2, 2014
- Jasper Design Automation, Inc.
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional property ranking
- Patent number 8,739,092
- Issue date May 27, 2014
- Jasper Design Automation, Inc.
- Asa Ben-Tzur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indexing behaviors and recipes of a circuit design
- Patent number 8,731,894
- Issue date May 20, 2014
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analysis of circuit designs via trace signatures
- Patent number 8,671,373
- Issue date Mar 11, 2014
- Jasper Design Automation, Inc.
- Craig Franklin Deaton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending waveforms of a circuit design
- Patent number 8,630,824
- Issue date Jan 14, 2014
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating properties for circuit designs
- Patent number 8,572,527
- Issue date Oct 29, 2013
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending a circuit design
- Patent number 8,527,911
- Issue date Sep 3, 2013
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating circuit design properties from signal traces
- Patent number 8,516,421
- Issue date Aug 20, 2013
- Jasper Design Automation, Inc.
- Asa Ben-Tzur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending a circuit design
- Patent number 8,458,621
- Issue date Jun 4, 2013
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
Information Patent Grant
Formal verification of deadlock property
- Patent number 8,381,148
- Issue date Feb 19, 2013
- Jasper Design Automation
- Lawrence Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static formal verification of a circuit design using properties def...
- Patent number 8,225,249
- Issue date Jul 17, 2012
- Jasper Design Automation, Inc.
- Johan Martensson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generalizing and inferring behaviors of a circuit design
- Patent number 8,205,187
- Issue date Jun 19, 2012
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debugging of counterexamples in formal verification
- Patent number 8,103,999
- Issue date Jan 24, 2012
- Jasper Design Automation, Inc.
- Johan Martensson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extracting, visualizing, and acting on inconsistencies between a ci...
- Patent number 7,895,552
- Issue date Feb 22, 2011
- Jasper Design Automation, Inc.
- Vigyan Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with multiple re...
- Patent number 7,647,572
- Issue date Jan 12, 2010
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive analysis and debugging of a circuit design during funct...
- Patent number 7,506,288
- Issue date Mar 17, 2009
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for determining and identifying signals that are...
- Patent number 7,437,694
- Issue date Oct 14, 2008
- Jasper Design Automation
- Lawrence Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Meaningful visualization of properties independent of a circuit design
- Patent number 7,421,668
- Issue date Sep 2, 2008
- Jasper Design Automation, Inc.
- Chung-Wah N. Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with counters
- Patent number 7,418,678
- Issue date Aug 26, 2008
- Jasper Design Automation, Inc.
- Chung-Wah N Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for measuring progress for formal verification of...
- Patent number 7,412,674
- Issue date Aug 12, 2008
- Jasper Design Automation
- Vigyan Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with datapaths
- Patent number 7,237,208
- Issue date Jun 26, 2007
- Jasper Design Automation, Inc.
- Chung-Wah N. Ip
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DATA PROPAGATION ANALYSIS FOR DEBUGGING A CIRCUIT DESIGN
- Publication number 20160283628
- Publication date Sep 29, 2016
- Jasper Design Automation, Inc.
- Fabiano Peixoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANIPULATION OF TRACES FOR DEBUGGING A CIRCUIT DESIGN
- Publication number 20150100932
- Publication date Apr 9, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANIPULATION OF TRACES FOR DEBUGGING BEHAVIORS OF A CIRCUIT DESIGN
- Publication number 20150100933
- Publication date Apr 9, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VISUALIZATION CONSTRAINTS FOR CIRCUIT DESIGNS
- Publication number 20150095862
- Publication date Apr 2, 2015
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING

Trademarklast 30 trademarks

Information Trademark
76595163 - PRECOGNITIVE ENGINE
- Serial number 76595163
- Filing date Jun 1, 2004
- JASPER DESIGN AUTOMATION, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76537760 - STATE SPACE TUNNELING
- Serial number 76537760
- Filing date Aug 4, 2003
- JASPER DESIGN AUTOMATION, INC.
- 42 - Scientific and technological services and research and design relating thereto
Information Trademark
76522381 - JASPER DESIGN AUTOMATION
- Serial number 76522381
- Registration number 3145861
- Filing date Jun 2, 2003
- JASPER DESIGN AUTOMATION, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76520967 - PCI EXPRESS PROOF KIT
- Serial number 76520967
- Filing date May 29, 2003
- JASPER DESIGN AUTOMATION, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76520969 - PRECOGNITIVE FORMAL VERIFICATION
- Serial number 76520969
- Filing date May 29, 2003
- JASPER DESIGN AUTOMATION, INC.
- 42 - Scientific and technological services and research and design relating thereto
Information Trademark
76520968 - JASPER PROOF KIT
- Serial number 76520968
- Filing date May 29, 2003
- JASPER DESIGN AUTOMATION, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76520966 - JASPERGOLD
- Serial number 76520966
- Registration number 2971960
- Filing date May 29, 2003
- JASPER DESIGN AUTOMATION, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76509830 - JASPER DESIGN AUTOMATION
- Serial number 76509830
- Filing date Apr 28, 2003
- TEMPUS FUGIT, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76509831 - JASPER DESIGN
- Serial number 76509831
- Filing date Apr 28, 2003
- TEMPUS FUGIT, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
76509832 - JASPER
- Serial number 76509832
- Registration number 3230138
- Filing date Apr 28, 2003
- TEMPUS FUGIT, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

JASPER DESIGN AUTOMATION AB

Organization

Business Address

Mailing Address

State Location

State of Incorporation

Patents Grantslast 30 patents

Functional property ranking

Security data path verification

Power aware retention flop list analysis and modification

Manipulation of traces for debugging a circuit design

Manipulation of traces for debugging behaviors of a circuit design

Visualization constraints for circuit designs

Veryifing low power functionality through RTL transformation

Constraining traces in formal verification

Indexing behaviors and recipes of a circuit design

Formal verification coverage metrics for circuit design properties

Functional property ranking

Indexing behaviors and recipes of a circuit design

Analysis of circuit designs via trace signatures

Comprehending waveforms of a circuit design

Generating properties for circuit designs

Comprehending a circuit design

Generating circuit design properties from signal traces

Comprehending a circuit design

Formal verification of deadlock property

Static formal verification of a circuit design using properties def...

Generalizing and inferring behaviors of a circuit design

Debugging of counterexamples in formal verification

Extracting, visualizing, and acting on inconsistencies between a ci...

Managing formal verification complexity of designs with multiple re...

Interactive analysis and debugging of a circuit design during funct...

System and method for determining and identifying signals that are...

Meaningful visualization of properties independent of a circuit design

Managing formal verification complexity of designs with counters

System and method for measuring progress for formal verification of...

Managing formal verification complexity of designs with datapaths

Patents Applicationslast 30 patents

DATA PROPAGATION ANALYSIS FOR DEBUGGING A CIRCUIT DESIGN

MANIPULATION OF TRACES FOR DEBUGGING A CIRCUIT DESIGN

MANIPULATION OF TRACES FOR DEBUGGING BEHAVIORS OF A CIRCUIT DESIGN

VISUALIZATION CONSTRAINTS FOR CIRCUIT DESIGNS

Trademarklast 30 trademarks

76595163 - PRECOGNITIVE ENGINE

76537760 - STATE SPACE TUNNELING

76522381 - JASPER DESIGN AUTOMATION

76520967 - PCI EXPRESS PROOF KIT

76520969 - PRECOGNITIVE FORMAL VERIFICATION

76520968 - JASPER PROOF KIT

76520966 - JASPERGOLD

76509830 - JASPER DESIGN AUTOMATION

76509831 - JASPER DESIGN

76509832 - JASPER