MegaMOS Corporation

Organization

San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Power transistor cells provided with reliable trenched source conta...
- Patent number 6,281,547
- Issue date Aug 28, 2001
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cost savings for manufacturing planar MOSFET devices achieved by im...
- Patent number 6,104,060
- Issue date Aug 15, 2000
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device fabrication with reduced masking steps
- Patent number 6,046,078
- Issue date Apr 4, 2000
- MegaMOS Corp.
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Punch-through prevention in trenched DMOS with poly-silicon layer c...
- Patent number 5,986,304
- Issue date Nov 16, 1999
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for device ruggedness improvement and on-resistance reductio...
- Patent number 5,930,630
- Issue date Jul 27, 1999
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power MOSFET device manufactured with simplified fabrication proces...
- Patent number 5,923,065
- Issue date Jul 13, 1999
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned and process-adjusted high density power transistor wit...
- Patent number 5,907,169
- Issue date May 25, 1999
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET structure and fabrication process implemented by forming dee...
- Patent number 5,895,951
- Issue date Apr 20, 1999
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-contact structure to prevent contact metal penetration through...
- Patent number 5,883,416
- Issue date Mar 16, 1999
- MegaMOS Corporation
- True-Lon Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Edge wrap-around protective extension for covering and protecting e...
- Patent number 5,883,410
- Issue date Mar 16, 1999
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mosfet termination design and core cell configuration to increase b...
- Patent number 5,877,529
- Issue date Mar 2, 1999
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure to provide effective channel-stop in termination areas fo...
- Patent number 5,877,528
- Issue date Mar 2, 1999
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cell topology for power transistors with increased packing density
- Patent number 5,763,914
- Issue date Jun 9, 1998
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with controlled breakdown protection
- Patent number 5,747,853
- Issue date May 5, 1998
- MegaMOS Corporation
- Koon Chong So
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET transistor cell manufactured with selectively implanted punc...
- Patent number 5,731,611
- Issue date Mar 24, 1998
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET structure and fabrication process for decreasing threshold v...
- Patent number 5,729,037
- Issue date Mar 17, 1998
- MegaMOS Corporation
- Fwu-Iuan Hshieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DMOS fabrication process implemented with reduced number of masks
- Patent number 5,668,026
- Issue date Sep 16, 1997
- MegaMOS Corporation
- True-Lon Lin
- H01 - BASIC ELECTRIC ELEMENTS

MegaMOS Corporation

Organization

Patents Grantslast 30 patents

Power transistor cells provided with reliable trenched source conta...

Cost savings for manufacturing planar MOSFET devices achieved by im...

Semiconductor device fabrication with reduced masking steps

Punch-through prevention in trenched DMOS with poly-silicon layer c...

Method for device ruggedness improvement and on-resistance reductio...

Power MOSFET device manufactured with simplified fabrication proces...

Self-aligned and process-adjusted high density power transistor wit...

MOSFET structure and fabrication process implemented by forming dee...

Gate-contact structure to prevent contact metal penetration through...

Edge wrap-around protective extension for covering and protecting e...

Mosfet termination design and core cell configuration to increase b...

Structure to provide effective channel-stop in termination areas fo...

Cell topology for power transistors with increased packing density

Semiconductor structure with controlled breakdown protection

MOSFET transistor cell manufactured with selectively implanted punc...

MOSFET structure and fabrication process for decreasing threshold v...

DMOS fabrication process implemented with reduced number of masks

Patents Applicationslast 30 patents

Trademarklast 30 trademarks