UPMEM

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Patents Grantslast 30 patents

Information Patent Grant
Methods and devices for bypassing the internal cache of an advanced...
- Patent number 11,494,308
- Issue date Nov 8, 2022
- UPMEM
- Jean-François Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for protecting a DRAM memory device from the row...
- Patent number 11,361,811
- Issue date Jun 14, 2022
- UPMEM
- Fabrice Devaux
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer correction logic for dram with integrated processor
- Patent number 11,049,544
- Issue date Jun 29, 2021
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing device within memory processing and narrow data ports
- Patent number 10,884,657
- Issue date Jan 5, 2021
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for protecting a DRAM memory device from the row...
- Patent number 10,885,966
- Issue date Jan 5, 2021
- UPMEM
- Fabrice Devaux
- G11 - INFORMATION STORAGE
Information Patent Grant
Combined instruction for addition and checking of terminals
- Patent number 10,817,288
- Issue date Oct 27, 2020
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit with integrated processor
- Patent number 10,324,870
- Issue date Jun 18, 2019
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A...
- Publication number 20240233800
- Publication date Jul 11, 2024
- UPMEM
- Fabrice DEVAUX
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR PROTECTING A MEMORY DEVICE FROM THE EF...
- Publication number 20240185910
- Publication date Jun 6, 2024
- UPMEM
- Fabrice DEVAUX
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A...
- Publication number 20240135981
- Publication date Apr 25, 2024
- UPMEM
- Fabrice DEVAUX
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS, AND CHIPS FOR SUC...
- Publication number 20230260968
- Publication date Aug 17, 2023
- UPMEM
- Fabrice DEVAUX
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND CIRCUIT FOR PROTECTING A DRAM MEMORY DEVICE FROM THE ROW...
- Publication number 20210398584
- Publication date Dec 23, 2021
- UPMEM
- Fabrice DEVAUX
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND DEVICES FOR BYPASSING THE INTERNAL CACHE OF AN ADVANCED...
- Publication number 20210349826
- Publication date Nov 11, 2021
- UPMEM
- Jean-François Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER CORRECTION LOGIC FOR DRAM WITH INTEGRATED PROCESSOR
- Publication number 20210012832
- Publication date Jan 14, 2021
- UPMEM
- Fabrice DEVAUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS
- Publication number 20190050223
- Publication date Feb 14, 2019
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING DEVICE WITH IN MEMORY PROCESSING AND NARROW DATA PORTS
- Publication number 20180260161
- Publication date Sep 13, 2018
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM CIRCUIT WITH INTEGRATED PROCESSOR
- Publication number 20180039586
- Publication date Feb 8, 2018
- UPMEM
- Fabrice Devaux
- G06 - COMPUTING CALCULATING COUNTING

Trademarklast 30 trademarks

Information Trademark
79225704 - UPMEM
- Serial number 79225704
- Registration number 5693949
- Filing date Dec 15, 2017
- UPMEM
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

Organization

Patents Grantslast 30 patents

Methods and devices for bypassing the internal cache of an advanced...

Method and circuit for protecting a DRAM memory device from the row...

Row hammer correction logic for dram with integrated processor

Computing device within memory processing and narrow data ports

Method and circuit for protecting a DRAM memory device from the row...

Combined instruction for addition and checking of terminals

Memory circuit with integrated processor

Patents Applicationslast 30 patents

MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A...

MEMORY DEVICE AND METHOD FOR PROTECTING A MEMORY DEVICE FROM THE EF...

MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A...

SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS, AND CHIPS FOR SUC...

METHOD AND CIRCUIT FOR PROTECTING A DRAM MEMORY DEVICE FROM THE ROW...

METHODS AND DEVICES FOR BYPASSING THE INTERNAL CACHE OF AN ADVANCED...

ROW HAMMER CORRECTION LOGIC FOR DRAM WITH INTEGRATED PROCESSOR

COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS

COMPUTING DEVICE WITH IN MEMORY PROCESSING AND NARROW DATA PORTS

DRAM CIRCUIT WITH INTEGRATED PROCESSOR

Trademarklast 30 trademarks

79225704 - UPMEM