Aaron J. Grenat

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Platform power manager for rack level power and thermal constraints
- Patent number 11,703,930
- Issue date Jul 18, 2023
- Advanced Micro Devices, Inc.
- Indrani Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Platform power manager for rack level power and thermal constraints
- Patent number 11,073,888
- Issue date Jul 27, 2021
- Advanced Micro Devices, Inc.
- Indrani Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating power supply voltages using reference measurements from...
- Patent number 10,060,955
- Issue date Aug 28, 2018
- Advanced Micro Devices, Inc.
- Aaron J. Grenat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Propagation simulation buffer for clock domain crossing
- Patent number 9,621,143
- Issue date Apr 11, 2017
- Advanced Micro Devices, Inc.
- Michael J. Osborn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low insertion delay clock doubler and integrated circuit clock dist...
- Patent number 9,372,499
- Issue date Jun 21, 2016
- Sriram Sambamurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuitry for debugging a power-gated circuit
- Patent number 8,595,563
- Issue date Nov 26, 2013
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G01 - MEASURING TESTING
Information Patent Grant
Clock domain crossing buffer
- Patent number 8,584,067
- Issue date Nov 12, 2013
- Advanced Micro Devices, Inc.
- Michael J. Osborn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-gated retention flops
- Patent number 8,381,163
- Issue date Feb 19, 2013
- Advanced Micro Devices, Inc.
- Jeremy P. Schreiber
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS
- Publication number 20230350480
- Publication date Nov 2, 2023
- ADVANCED MICRO DEVICES, INC.
- Indrani Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS
- Publication number 20210349517
- Publication date Nov 11, 2021
- ADVANCED MICRO DEVICES, INC.
- Indrani Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS
- Publication number 20200379544
- Publication date Dec 3, 2020
- ADVANCED MICRO DEVICES, INC.
- Indrani Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALIBRATING A POWER SUPPLY USING POWER SUPPLY MONITORS
- Publication number 20150378411
- Publication date Dec 31, 2015
- Advanced Micro Devices, Inc.
- Aaron J. Grenat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW INSERTION DELAY CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DIST...
- Publication number 20150205323
- Publication date Jul 23, 2015
- Advanced Micro Devices, Inc.
- Sriram Sambamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROPAGATION SIMULATION BUFFER
- Publication number 20140062555
- Publication date Mar 6, 2014
- Advanced Micro Devices, Inc.
- Michael J. Osborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT
- Publication number 20130024829
- Publication date Jan 24, 2013
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G01 - MEASURING TESTING
Information Patent Application
POWER-GATED RETENTION FLOPS
- Publication number 20120131526
- Publication date May 24, 2012
- Jeremy P. Schreiber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK DOMAIN CROSSING BUFFER
- Publication number 20120110529
- Publication date May 3, 2012
- Michael J. Osborn
- G06 - COMPUTING CALCULATING COUNTING

Aaron J. Grenat

Person

Patents Grantslast 30 patents

Platform power manager for rack level power and thermal constraints

Platform power manager for rack level power and thermal constraints

Calibrating power supply voltages using reference measurements from...

Propagation simulation buffer for clock domain crossing

Low insertion delay clock doubler and integrated circuit clock dist...

Method and circuitry for debugging a power-gated circuit

Clock domain crossing buffer

Power-gated retention flops

Patents Applicationslast 30 patents

PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS

PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS

PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS

CALIBRATING A POWER SUPPLY USING POWER SUPPLY MONITORS

LOW INSERTION DELAY CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DIST...

PROPAGATION SIMULATION BUFFER

METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT

POWER-GATED RETENTION FLOPS

CLOCK DOMAIN CROSSING BUFFER