Aaron J. Smith

Person

Everett, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Implicit program order
- Patent number 11,977,891
- Issue date May 7, 2024
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction block allocation
- Patent number 11,755,484
- Issue date Sep 12, 2023
- Microsoft Technology Licensing, LLC
- Jan S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order block-based processors and instruction schedulers usin...
- Patent number 11,687,345
- Issue date Jun 27, 2023
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation and use of memory access instruction order encodings
- Patent number 11,681,531
- Issue date Jun 20, 2023
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid block-based processor and custom function blocks
- Patent number 11,449,342
- Issue date Sep 20, 2022
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block-based processor core composition register
- Patent number 11,126,433
- Issue date Sep 21, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental scheduler for out-of-order block ISA processors
- Patent number 11,106,467
- Issue date Aug 31, 2021
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupled processor instruction window and operand buffer
- Patent number 11,048,517
- Issue date Jun 29, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distinct system registers for logical processors
- Patent number 11,016,770
- Issue date May 25, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dense read encoding for dataflow ISA
- Patent number 10,936,316
- Issue date Mar 2, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register read/write ordering
- Patent number 10,871,967
- Issue date Dec 22, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug support for block-based processor
- Patent number 10,776,115
- Issue date Sep 15, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block-based processor including topology and control registers to i...
- Patent number 10,768,936
- Issue date Sep 8, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initiating instruction block execution using a register access inst...
- Patent number 10,678,544
- Issue date Jun 9, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Free form expression accelerator with thread length-based thread as...
- Patent number 10,606,651
- Issue date Mar 31, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Broadcast channel architectures for block-based processors
- Patent number 10,452,399
- Issue date Oct 22, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimodal targets in a block-based processor
- Patent number 10,445,097
- Issue date Oct 15, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoding information about a group of instructions including a size...
- Patent number 10,409,599
- Issue date Sep 10, 2019
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying branch targets
- Patent number 10,409,606
- Issue date Sep 10, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupled processor instruction window and operand buffer
- Patent number 10,346,168
- Issue date Jul 9, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write nullification
- Patent number 10,198,263
- Issue date Feb 5, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic generation of null instructions
- Patent number 10,180,840
- Issue date Jan 15, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Explicit instruction scheduler state information for a processor
- Patent number 10,175,988
- Issue date Jan 8, 2019
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing an encoding format field to interpret header information...
- Patent number 10,169,044
- Issue date Jan 1, 2019
- Microsoft Technology Licensing, LLC
- Doug Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction block address register
- Patent number 10,095,519
- Issue date Oct 9, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store nullification in the target field
- Patent number 10,061,584
- Issue date Aug 28, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-nullification
- Patent number 10,031,756
- Issue date Jul 24, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping instruction blocks based on block size
- Patent number 9,952,867
- Issue date Apr 24, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Age-based management of instruction blocks in a processor instructi...
- Patent number 9,946,548
- Issue date Apr 17, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of decoded instructions
- Patent number 9,940,136
- Issue date Apr 10, 2018
- Microsoft Technology Licensing, LLC
- Douglas Christopher Burger
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER
- Publication number 20190310852
- Publication date Oct 10, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OFFLINE ACTIVATION FOR APPLICATION(S) INSTALLED ON A COMPUTING DEVICE
- Publication number 20190026442
- Publication date Jan 24, 2019
- Microsoft Technology Licensing, LLC
- Brian Perlman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-NULLIFICATION
- Publication number 20180329708
- Publication date Nov 15, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL REGISTER FILE FOR A PROCESSOR
- Publication number 20180032335
- Publication date Feb 1, 2018
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER BLOCK-BASED PROCESSOR
- Publication number 20180032344
- Publication date Feb 1, 2018
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR
- Publication number 20170371659
- Publication date Dec 28, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES
- Publication number 20170371660
- Publication date Dec 28, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR
- Publication number 20170315812
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS
- Publication number 20170315814
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL SCHEDULER FOR OUT-OF-ORDER BLOCK ISA PROCESSORS
- Publication number 20170315813
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID BLOCK-BASED PROCESSOR AND CUSTOM FUNCTION BLOCKS
- Publication number 20170315815
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTINCT SYSTEM REGISTERS FOR LOGICAL PROCESSORS
- Publication number 20170083316
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORE NULLIFICATION IN THE TARGET FIELD
- Publication number 20170083328
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER
- Publication number 20170083334
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING ASSOCIATED WITH PREDICATED STORE INSTRUCTIONS
- Publication number 20170083339
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIATING INSTRUCTION BLOCK EXECUTION USING A REGISTER ACCESS INST...
- Publication number 20170083314
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS
- Publication number 20170083324
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block-based processor core composition register
- Publication number 20170083315
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configuring modes of processor operation
- Publication number 20170083318
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION AND USE OF BLOCK BRANCH METADATA
- Publication number 20170083319
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIMODAL TARGETS IN A BLOCK-BASED PROCESSOR
- Publication number 20170083322
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic generation of null instructions
- Publication number 20170083325
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE NULLIFICATION
- Publication number 20170083329
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-NULLIFICATION
- Publication number 20170083330
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS
- Publication number 20170083331
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER READ/WRITE ORDERING
- Publication number 20170083326
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLICIT PROGRAM ORDER
- Publication number 20170083327
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BROADCAST CHANNEL ARCHITECTURES FOR BLOCK-BASED PROCESSORS
- Publication number 20170083335
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR
- Publication number 20170083431
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICATED READ INSTRUCTIONS
- Publication number 20170083320
- Publication date Mar 23, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING

Aaron J. Smith

Person

Patents Grantslast 30 patents

Implicit program order

Instruction block allocation

Out-of-order block-based processors and instruction schedulers usin...

Generation and use of memory access instruction order encodings

Hybrid block-based processor and custom function blocks

Block-based processor core composition register

Incremental scheduler for out-of-order block ISA processors

Decoupled processor instruction window and operand buffer

Distinct system registers for logical processors

Dense read encoding for dataflow ISA

Register read/write ordering

Debug support for block-based processor

Block-based processor including topology and control registers to i...

Initiating instruction block execution using a register access inst...

Free form expression accelerator with thread length-based thread as...

Broadcast channel architectures for block-based processors

Multimodal targets in a block-based processor

Decoding information about a group of instructions including a size...

Verifying branch targets

Decoupled processor instruction window and operand buffer

Write nullification

Dynamic generation of null instructions

Explicit instruction scheduler state information for a processor

Processing an encoding format field to interpret header information...

Instruction block address register

Store nullification in the target field

Multi-nullification

Mapping instruction blocks based on block size

Age-based management of instruction blocks in a processor instructi...

Reuse of decoded instructions

Patents Applicationslast 30 patents

DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER

OFFLINE ACTIVATION FOR APPLICATION(S) INSTALLED ON A COMPUTING DEVICE

MULTI-NULLIFICATION

TRANSACTIONAL REGISTER FILE FOR A PROCESSOR

OUT-OF-ORDER BLOCK-BASED PROCESSOR

LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR

LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES

PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR

OUT-OF-ORDER BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS

INCREMENTAL SCHEDULER FOR OUT-OF-ORDER BLOCK ISA PROCESSORS

HYBRID BLOCK-BASED PROCESSOR AND CUSTOM FUNCTION BLOCKS

DISTINCT SYSTEM REGISTERS FOR LOGICAL PROCESSORS

STORE NULLIFICATION IN THE TARGET FIELD

BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER

PREFETCHING ASSOCIATED WITH PREDICATED STORE INSTRUCTIONS

INITIATING INSTRUCTION BLOCK EXECUTION USING A REGISTER ACCESS INST...

GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS

Block-based processor core composition register

Configuring modes of processor operation

GENERATION AND USE OF BLOCK BRANCH METADATA

MULTIMODAL TARGETS IN A BLOCK-BASED PROCESSOR

Dynamic generation of null instructions

WRITE NULLIFICATION

MULTI-NULLIFICATION

MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS

REGISTER READ/WRITE ORDERING

IMPLICIT PROGRAM ORDER

BROADCAST CHANNEL ARCHITECTURES FOR BLOCK-BASED PROCESSORS

DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR

PREDICATED READ INSTRUCTIONS