Aaron K. Martin

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Duty cycle correction system and low dropout (LDO) regulator based...
- Patent number 11,722,128
- Issue date Aug 8, 2023
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duty cycle correction system and low dropout (LDO) regulator based...
- Patent number 11,070,200
- Issue date Jul 20, 2021
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual power I/O transmitter
- Patent number 10,923,164
- Issue date Feb 16, 2021
- Intel Corporation
- Hariprasath Venkatram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic reconfigurable dual power I/O receiver
- Patent number 10,672,438
- Issue date Jun 2, 2020
- Intel Corporation
- Mohammed G. Mostofa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable clocking architecture
- Patent number 10,134,463
- Issue date Nov 20, 2018
- Intel Corporation
- Mozhgan Mansuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed signal low dropout voltage regulator with low output impedance
- Patent number 10,025,333
- Issue date Jul 17, 2018
- Intel Corporation
- Moonkyun Maeng
- G05 - CONTROLLING REGULATING
Information Patent Grant
Converged adaptive compensation scheme
- Patent number 10,007,749
- Issue date Jun 26, 2018
- Intel Corporation
- Roger K. Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable clocking architecture
- Patent number 9,786,353
- Issue date Oct 10, 2017
- Intel Corporation
- Mozhgan Mansuri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interconnection of a packaged chip to a die in a package utilizing...
- Patent number 9,536,863
- Issue date Jan 3, 2017
- Intel Corporation
- Todd A. Hinck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
I/O driver transmit swing control
- Patent number 9,374,004
- Issue date Jun 21, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory receiver circuit for use with memory of different characteri...
- Patent number 9,355,693
- Issue date May 31, 2016
- Intel Corporation
- Moonkyun Maeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Transceiver clock architecture with transmit PLL and receive slave...
- Patent number 9,237,000
- Issue date Jan 12, 2016
- Intel Corporation
- Aaron Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low swing voltage mode driver
- Patent number 9,152,257
- Issue date Oct 6, 2015
- Intel Corporation
- James A. McCall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transmitter with voltage and current mode drivers
- Patent number 9,024,665
- Issue date May 5, 2015
- Intel Corporation
- Derek M. Conrow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pre-distorting a transmitted signal for offset cancellation
- Patent number 8,213,887
- Issue date Jul 3, 2012
- Intel Corporation
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for delay locked loop relock mode
- Patent number 8,144,529
- Issue date Mar 27, 2012
- Intel Corporation
- Hsiao-Ching Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-distorting a transmitted signal for offset cancellation
- Patent number 7,979,039
- Issue date Jul 12, 2011
- Intel Corporation
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,954,001
- Issue date May 31, 2011
- Intel Corporation
- Aaron K. Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed receiver
- Patent number 7,756,495
- Issue date Jul 13, 2010
- Intel Corporation
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock deskewing method, apparatus, and system
- Patent number 7,668,524
- Issue date Feb 23, 2010
- Intel Corporation
- Hon-Mo Raymond Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse amplitude modulated system with reduced intersymbol interference
- Patent number 7,653,165
- Issue date Jan 26, 2010
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Defining pin functionality at device power on
- Patent number 7,644,250
- Issue date Jan 5, 2010
- Intel Corporation
- David J. Zimmerman
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit to syncrhonize the phase of a distributed clock signal with...
- Patent number 7,620,134
- Issue date Nov 17, 2009
- Intel Corporation
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clocking architecture using a bidirectional clock port
- Patent number 7,555,670
- Issue date Jun 30, 2009
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable delay for clock phase error correction
- Patent number 7,545,194
- Issue date Jun 9, 2009
- Intel Corporation
- Suwei Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock recovery apparatus, method, and system
- Patent number 7,457,393
- Issue date Nov 25, 2008
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receive clock deskewing method, apparatus, and system
- Patent number 7,439,788
- Issue date Oct 21, 2008
- Intel Corporation
- Hon-Mo Raymond Law
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Crosstalk reduction method, apparatus, and system
- Patent number 7,412,221
- Issue date Aug 12, 2008
- Intel Corporation
- Ravindran Mohanavelu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,401,246
- Issue date Jul 15, 2008
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse amplitude modulated system with reduced intersymbol interference
- Patent number 7,391,834
- Issue date Jun 24, 2008
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...
- Publication number 20210320652
- Publication date Oct 14, 2021
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL POWER I/O TRANSMITTER
- Publication number 20200105317
- Publication date Apr 2, 2020
- Intel Corporation
- Hariprasath VENKATRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER
- Publication number 20200105319
- Publication date Apr 2, 2020
- Intel Corporation
- Mohammed G. Mostofa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...
- Publication number 20200106430
- Publication date Apr 2, 2020
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CLOCKING ARCHITECTURE
- Publication number 20180102162
- Publication date Apr 12, 2018
- Intel Corporation
- Mozhgan Mansuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CLOCKING ARCHITECTURE
- Publication number 20170243627
- Publication date Aug 24, 2017
- Intel Corporation
- Mozhgan Mansuri
- G11 - INFORMATION STORAGE
Information Patent Application
LOW SWING VOLTAGE MODE DRIVER
- Publication number 20160285451
- Publication date Sep 29, 2016
- JAMES A. MCCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED SIGNAL LOW DROPOUT VOLTAGE REGULATOR WITH LOW OUTPUT IMPEDANCE
- Publication number 20160259354
- Publication date Sep 8, 2016
- Intel Corporation
- Moonkyun Maeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Converged Adaptive Compensation Scheme
- Publication number 20160087918
- Publication date Mar 24, 2016
- Roger K. Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O DRIVER TRANSMIT SWING CONTROL
- Publication number 20150002408
- Publication date Jan 1, 2015
- CHRISTOPHER P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY RECEIVER CIRCUIT FOR USE WITH MEMORY OF DIFFERENT CHARACTERI...
- Publication number 20140269130
- Publication date Sep 18, 2014
- Moonkyun Maeng
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSMITTER WITH VOLTAGE AND CURRENT MODE DRIVERS
- Publication number 20140266320
- Publication date Sep 18, 2014
- Derek M. Conrow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW SWING VOLTAGE MODE DRIVER
- Publication number 20140184523
- Publication date Jul 3, 2014
- JAMES A. MCCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION OF A PACKAGED CHIP TO A DIE IN A PACKAGE UTILIZING...
- Publication number 20130313709
- Publication date Nov 28, 2013
- Todd A. Hinck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pre-Distorting A Transmitted Signal For Offset Cancellation
- Publication number 20110255581
- Publication date Oct 20, 2011
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR DELAY LOCKED LOOP RELOCK MODE
- Publication number 20100246294
- Publication date Sep 30, 2010
- Hsiao-Ching Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-distorting a transmitted signal for offset cancellation
- Publication number 20090079484
- Publication date Mar 26, 2009
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM
- Publication number 20080244303
- Publication date Oct 2, 2008
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pulse amplitude modulated system with reduced intersymbol interference
- Publication number 20080181331
- Publication date Jul 31, 2008
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Circuit to syncrhonize the phase of a distributed clock signal with...
- Publication number 20080049883
- Publication date Feb 28, 2008
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable delay for clock phase error correction
- Publication number 20080012653
- Publication date Jan 17, 2008
- Intel Corporation
- Suwei Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Defining pin functionality at device power on
- Publication number 20080002336
- Publication date Jan 3, 2008
- David J. Zimmerman
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Clock error detection circuits, methods, and systems
- Publication number 20080001637
- Publication date Jan 3, 2008
- Suwei Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Transceiver clock architecture with transmit PLL and receive slave...
- Publication number 20070291828
- Publication date Dec 20, 2007
- Aaron Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock deskewing method, apparatus, and system
- Publication number 20070149142
- Publication date Jun 28, 2007
- Intel Corporation
- Hon-Mo Raymond Law
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Receive clock deskewing method, apparatus, and system
- Publication number 20070146035
- Publication date Jun 28, 2007
- Intel Corporation
- Hon-Mo Raymond Law
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clocking architecture using a bi-directional reference clock
- Publication number 20070091712
- Publication date Apr 26, 2007
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed receiver
- Publication number 20070072568
- Publication date Mar 29, 2007
- Taner Sumesaglam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Nibble de-skew method, apparatus, and system
- Publication number 20070006011
- Publication date Jan 4, 2007
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage mode driver with current mode equalization
- Publication number 20060290439
- Publication date Dec 28, 2006
- Intel Corporation
- Aaron K. Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Aaron K. Martin

Person

Patents Grantslast 30 patents

Duty cycle correction system and low dropout (LDO) regulator based...

Duty cycle correction system and low dropout (LDO) regulator based...

Dual power I/O transmitter

Dynamic reconfigurable dual power I/O receiver

Reconfigurable clocking architecture

Mixed signal low dropout voltage regulator with low output impedance

Converged adaptive compensation scheme

Reconfigurable clocking architecture

Interconnection of a packaged chip to a die in a package utilizing...

I/O driver transmit swing control

Memory receiver circuit for use with memory of different characteri...

Transceiver clock architecture with transmit PLL and receive slave...

Low swing voltage mode driver

Transmitter with voltage and current mode drivers

Pre-distorting a transmitted signal for offset cancellation

System and method for delay locked loop relock mode

Pre-distorting a transmitted signal for offset cancellation

Nibble de-skew method, apparatus, and system

High speed receiver

Clock deskewing method, apparatus, and system

Pulse amplitude modulated system with reduced intersymbol interference

Defining pin functionality at device power on

Circuit to syncrhonize the phase of a distributed clock signal with...

Clocking architecture using a bidirectional clock port

Programmable delay for clock phase error correction

Clock recovery apparatus, method, and system

Receive clock deskewing method, apparatus, and system

Crosstalk reduction method, apparatus, and system

Nibble de-skew method, apparatus, and system

Pulse amplitude modulated system with reduced intersymbol interference

Patents Applicationslast 30 patents

DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...

DUAL POWER I/O TRANSMITTER

DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER

DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...

RECONFIGURABLE CLOCKING ARCHITECTURE

RECONFIGURABLE CLOCKING ARCHITECTURE

LOW SWING VOLTAGE MODE DRIVER

MIXED SIGNAL LOW DROPOUT VOLTAGE REGULATOR WITH LOW OUTPUT IMPEDANCE

Converged Adaptive Compensation Scheme

I/O DRIVER TRANSMIT SWING CONTROL

MEMORY RECEIVER CIRCUIT FOR USE WITH MEMORY OF DIFFERENT CHARACTERI...

TRANSMITTER WITH VOLTAGE AND CURRENT MODE DRIVERS

LOW SWING VOLTAGE MODE DRIVER

INTERCONNECTION OF A PACKAGED CHIP TO A DIE IN A PACKAGE UTILIZING...

Pre-Distorting A Transmitted Signal For Offset Cancellation

SYSTEM AND METHOD FOR DELAY LOCKED LOOP RELOCK MODE

Pre-distorting a transmitted signal for offset cancellation

NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM

Pulse amplitude modulated system with reduced intersymbol interference

Circuit to syncrhonize the phase of a distributed clock signal with...

Programmable delay for clock phase error correction

Defining pin functionality at device power on

Clock error detection circuits, methods, and systems

Transceiver clock architecture with transmit PLL and receive slave...

Clock deskewing method, apparatus, and system

Receive clock deskewing method, apparatus, and system

Clocking architecture using a bi-directional reference clock

High speed receiver

Nibble de-skew method, apparatus, and system

Voltage mode driver with current mode equalization