Aaron Ng

Person

Belmont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reconfigurable neural engine with extensible instruction set archit...
- Patent number 12,079,158
- Issue date Sep 3, 2024
- Xilinx, Inc.
- Sanket Pandit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning runtime library for neural network acceleration
- Patent number 11,694,066
- Issue date Jul 4, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer neural network processing by a neural network accelerat...
- Patent number 11,620,490
- Issue date Apr 4, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network processing system having host controlled kernel accl...
- Patent number 11,568,218
- Issue date Jan 31, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host-directed multi-layer neural network processing via per-layer w...
- Patent number 11,429,848
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image preprocessing for generalized image processing
- Patent number 11,386,644
- Issue date Jul 12, 2022
- Xilinx, Inc.
- Elliott Delaye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network processing system having multiple processors and a n...
- Patent number 11,222,256
- Issue date Jan 11, 2022
- Xilinx, Inc.
- Xiao Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-targetable interface for data exchange between heterogeneous sys...
- Patent number 11,204,747
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-defined buffer/transposer for general matrix multiplicatio...
- Patent number 11,036,827
- Issue date Jun 15, 2021
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline image preprocessing for convolution operations using a matri...
- Patent number 10,984,500
- Issue date Apr 20, 2021
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-driven design optimization for fixed-point multiply-accumu...
- Patent number 10,943,039
- Issue date Mar 9, 2021
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix processing circuitry
- Patent number 10,936,311
- Issue date Mar 2, 2021
- Xilinx, Inc.
- Ling Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-driven design optimization for mapping between floating-po...
- Patent number 10,678,509
- Issue date Jun 9, 2020
- Xilinx, Inc.
- Sean Settle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data format suitable for fast massively parallel general matrix mul...
- Patent number 10,515,135
- Issue date Dec 24, 2019
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline image preprocessing for convolution operations using a matri...
- Patent number 10,460,416
- Issue date Oct 29, 2019
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing closure of circuit designs for integrated circuits
- Patent number 10,366,201
- Issue date Jul 30, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-defined memory bandwidth reduction by hierarchical stream...
- Patent number 10,354,733
- Issue date Jul 16, 2019
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network based physical synthesis for circuit designs
- Patent number 10,192,016
- Issue date Jan 29, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fanout optimization to facilitate timing improvement in circuit des...
- Patent number 9,965,581
- Issue date May 8, 2018
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuit design flow using timing-driven pip...
- Patent number 9,836,568
- Issue date Dec 5, 2017
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-routing structural netlist optimization for circuit designs
- Patent number 9,646,126
- Issue date May 9, 2017
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource mapping of functional areas on an integrated circuit
- Patent number 7,840,919
- Issue date Nov 23, 2010
- Xilinx, Inc.
- Qiang Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING...
- Publication number 20240069511
- Publication date Feb 29, 2024
- Xilinx, Inc.
- Jorn Tuyls
- G05 - CONTROLLING REGULATING
Information Patent Application
INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL
- Publication number 20240045692
- Publication date Feb 8, 2024
- Xilinx, Inc.
- Xiao Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHIT...
- Publication number 20240028556
- Publication date Jan 25, 2024
- Xilinx, Inc.
- Sanket Pandit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELE...
- Publication number 20230297824
- Publication date Sep 21, 2023
- Xilinx, Inc.
- Rajeev Patwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING DEPLOYMENT PLATFORM
- Publication number 20230244966
- Publication date Aug 3, 2023
- Xilinx, Inc.
- Varun Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LAYER NEURAL NETWORK PROCESSING BY A NEURAL NETWORK ACCELERAT...
- Publication number 20190114529
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING RUNTIME LIBRARY FOR NEURAL NETWORK ACCELERATION
- Publication number 20190114533
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK PROCESSING SYSTEM HAVING HOST CONTROLLED KERNEL ACCL...
- Publication number 20190114535
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND A N...
- Publication number 20190114534
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Xiao Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST-DIRECTED MULTI-LAYER NEURAL NETWORK PROCESSING VIA PER-LAYER W...
- Publication number 20190114538
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMAGE PREPROCESSING FOR GENERALIZED IMAGE PROCESSING
- Publication number 20190114499
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Elliott Delaye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS
- Publication number 20180203956
- Publication date Jul 19, 2018
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Reconfigurable neural engine with extensible instruction set archit...

Machine learning runtime library for neural network acceleration

Multi-layer neural network processing by a neural network accelerat...

Neural network processing system having host controlled kernel accl...

Host-directed multi-layer neural network processing via per-layer w...

Image preprocessing for generalized image processing

Neural network processing system having multiple processors and a n...

Re-targetable interface for data exchange between heterogeneous sys...

Software-defined buffer/transposer for general matrix multiplicatio...

Inline image preprocessing for convolution operations using a matri...

Software-driven design optimization for fixed-point multiply-accumu...

Sparse matrix processing circuitry

Software-driven design optimization for mapping between floating-po...

Data format suitable for fast massively parallel general matrix mul...

Inline image preprocessing for convolution operations using a matri...

Timing closure of circuit designs for integrated circuits

Software-defined memory bandwidth reduction by hierarchical stream...

Neural network based physical synthesis for circuit designs

Fanout optimization to facilitate timing improvement in circuit des...

Programmable integrated circuit design flow using timing-driven pip...

Post-routing structural netlist optimization for circuit designs

Resource mapping of functional areas on an integrated circuit

Patents Applicationslast 30 patents

INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING...

INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL

RECONFIGURABLE NEURAL ENGINE WITH EXTENSIBLE INSTRUCTION SET ARCHIT...

PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELE...

MACHINE LEARNING DEPLOYMENT PLATFORM

MULTI-LAYER NEURAL NETWORK PROCESSING BY A NEURAL NETWORK ACCELERAT...

MACHINE LEARNING RUNTIME LIBRARY FOR NEURAL NETWORK ACCELERATION

NEURAL NETWORK PROCESSING SYSTEM HAVING HOST CONTROLLED KERNEL ACCL...

NEURAL NETWORK PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND A N...

HOST-DIRECTED MULTI-LAYER NEURAL NETWORK PROCESSING VIA PER-LAYER W...

IMAGE PREPROCESSING FOR GENERALIZED IMAGE PROCESSING

NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS