Abdel Hakim S. Alhussien

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Read disturb detection based on dynamic bit error rate estimation
- Patent number 10,482,983
- Issue date Nov 19, 2019
- Seagate Technology LLC
- Abdel Hakim Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open block handling to reduce write errors
- Patent number 10,268,404
- Issue date Apr 23, 2019
- Seagate Technology LLC
- Abdel Hakim Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open block handling to reduce write errors
- Patent number 9,933,963
- Issue date Apr 3, 2018
- Seagate Technology
- Abdel Hakim Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tier detection and decoding in flash memories
- Patent number 9,898,361
- Issue date Feb 20, 2018
- Seagate Technology LLC
- Erich F. Haratsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Priori information based post-processing in low-density parity-chec...
- Patent number 9,513,989
- Issue date Dec 6, 2016
- Seagate Technology LLC
- Zhengang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Incremental programming pulse optimization to reduce write errors
- Patent number 9,396,807
- Issue date Jul 19, 2016
- Seagate Technology LLC
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Log-likelihood ratio (LLR) dampening in low-density parity-check (L...
- Patent number 9,337,865
- Issue date May 10, 2016
- Seagate Technology LLC
- Earl T. Cohen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Detection/erasure of random write errors using converged hard decis...
- Patent number 9,298,547
- Issue date Mar 29, 2016
- Seagate Technology LLC
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Detection and decoding in flash memories using correlation of neigh...
- Patent number 9,292,377
- Issue date Mar 22, 2016
- Seagate Technology LLC
- Abdel Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for directed soft data perturbation in layered...
- Patent number 9,184,954
- Issue date Nov 10, 2015
- Seagate Technology LLC
- Abdel Hakim S. Alhussien
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encoding and decoding in flash memories using convolutional-type lo...
- Patent number 9,106,264
- Issue date Aug 11, 2015
- Abdel Hakim S. Alhussien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Detection and decoding in flash memories with selective binary and...
- Patent number 9,086,984
- Issue date Jul 21, 2015
- Seagate Technology LLC
- Abdel Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory reference voltage detection with tracking of cross-poi...
- Patent number 9,036,413
- Issue date May 19, 2015
- Seagate Technology LLC
- Yunxiang Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory read retry using histograms
- Patent number 8,953,373
- Issue date Feb 10, 2015
- LSI Corporation
- Yunxiang Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensation loop for read voltage adaptation
- Patent number 8,879,324
- Issue date Nov 4, 2014
- LSI Corporation
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold optimization for flash memory
- Patent number 8,848,439
- Issue date Sep 30, 2014
- LSI Corporation
- Fan Zhang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
OPEN BLOCK HANDLING TO REDUCE WRITE ERRORS
- Publication number 20180253240
- Publication date Sep 6, 2018
- Seagate Technology LLC
- Abdel Hakim Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read Disturb Detection Based on Dynamic Bit Error Rate Estimation
- Publication number 20180182465
- Publication date Jun 28, 2018
- Seagate Technology LLC
- Abdel Hakim Alhussien
- G11 - INFORMATION STORAGE
Information Patent Application
Priori Information Based Post-Processing in Low-Density Parity-Chec...
- Publication number 20170085277
- Publication date Mar 23, 2017
- Seagate Technology LLC
- Zhengang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detection/Erasure of Random Write Errors Using Converged Hard Decis...
- Publication number 20150135032
- Publication date May 14, 2015
- LSI Corporation
- Abdel-Hakim S. Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Incremental Programming Pulse Optimization to Reduce Write Errors
- Publication number 20150131373
- Publication date May 14, 2015
- LSI Corporation
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POI...
- Publication number 20150092489
- Publication date Apr 2, 2015
- LSI Corporation
- Yunxiang Wu
- G11 - INFORMATION STORAGE
Information Patent Application
Priori Information Based Post-Processing in Low-Density Parity-Chec...
- Publication number 20140298131
- Publication date Oct 2, 2014
- LSI Corporation
- Zhengang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compensation Loop for Read Voltage Adaptation
- Publication number 20140219028
- Publication date Aug 7, 2014
- LSI Corporation
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Application
LOG-LIKELIHOOD RATIO (LLR) DAMPENING IN LOW-DENSITY PARITY-CHECK (L...
- Publication number 20140143637
- Publication date May 22, 2014
- Earl T. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THRESHOLD OPTIMIZATION FOR FLASH MEMORY
- Publication number 20140056067
- Publication date Feb 27, 2014
- LSI CORPORATION
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGH...
- Publication number 20130185599
- Publication date Jul 18, 2013
- LSI Corporation
- Abdel Hakim S. Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TIER DETECTION AND DECODING IN FLASH MEMORIES
- Publication number 20130185598
- Publication date Jul 18, 2013
- Erich F. Haratsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LO...
- Publication number 20130145238
- Publication date Jun 6, 2013
- LSI Corporation
- Abdel Hakim S. Alhussien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION AND DECODING IN FLASH MEMORIES WITH SELECTIVE BINARY AND...
- Publication number 20130145235
- Publication date Jun 6, 2013
- LSI Corporation
- Abdel Hakim S. Alhussien
- G06 - COMPUTING CALCULATING COUNTING

Abdel Hakim S. Alhussien

Person

Patents Grantslast 30 patents

Read disturb detection based on dynamic bit error rate estimation

Open block handling to reduce write errors

Open block handling to reduce write errors

Multi-tier detection and decoding in flash memories

Priori information based post-processing in low-density parity-chec...

Incremental programming pulse optimization to reduce write errors

Log-likelihood ratio (LLR) dampening in low-density parity-check (L...

Detection/erasure of random write errors using converged hard decis...

Detection and decoding in flash memories using correlation of neigh...

Systems and methods for directed soft data perturbation in layered...

Encoding and decoding in flash memories using convolutional-type lo...

Detection and decoding in flash memories with selective binary and...

Flash memory reference voltage detection with tracking of cross-poi...

Flash memory read retry using histograms

Compensation loop for read voltage adaptation

Threshold optimization for flash memory

Patents Applicationslast 30 patents

OPEN BLOCK HANDLING TO REDUCE WRITE ERRORS

Read Disturb Detection Based on Dynamic Bit Error Rate Estimation

Priori Information Based Post-Processing in Low-Density Parity-Chec...

Detection/Erasure of Random Write Errors Using Converged Hard Decis...

Incremental Programming Pulse Optimization to Reduce Write Errors

FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POI...

Priori Information Based Post-Processing in Low-Density Parity-Chec...

Compensation Loop for Read Voltage Adaptation

LOG-LIKELIHOOD RATIO (LLR) DAMPENING IN LOW-DENSITY PARITY-CHECK (L...

THRESHOLD OPTIMIZATION FOR FLASH MEMORY

DETECTION AND DECODING IN FLASH MEMORIES USING CORRELATION OF NEIGH...

MULTI-TIER DETECTION AND DECODING IN FLASH MEMORIES

ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LO...

DETECTION AND DECODING IN FLASH MEMORIES WITH SELECTIVE BINARY AND...