Abhijeet A. Chachad

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Write control for read-modify-write operations in cache memory
- Patent number 12,001,282
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-requestor memory access pipeline and arbiter
- Patent number 12,001,351
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,977,491
- Issue date May 7, 2024
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 11,940,918
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write streaming with cache write acknowledgment in a processor
- Patent number 11,921,637
- Issue date Mar 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller with caching and non-caching modes
- Patent number 11,907,753
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 11,816,032
- Issue date Nov 14, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with wire reduction and physical congest...
- Patent number 11,803,505
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 11,789,868
- Issue date Oct 17, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implied fence on stream open
- Patent number 11,782,718
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting codes for multi-master memory controller
- Patent number 11,768,733
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merging data for write allocate
- Patent number 11,762,683
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 11,740,930
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache security
- Patent number 11,720,495
- Issue date Aug 8, 2023
- Texas Instmments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shadow caches for level 2 cache controller
- Patent number 11,714,754
- Issue date Aug 1, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence for memory controller
- Patent number 11,687,457
- Issue date Jun 27, 2023
- Texas Intruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 11,675,660
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 11,675,700
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,620,236
- Issue date Apr 4, 2023
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined read-modify-write operations in cache memory
- Patent number 11,609,818
- Issue date Mar 21, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 11,580,024
- Issue date Feb 14, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 11,567,874
- Issue date Jan 31, 2023
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead priority collection to support priority elevation
- Patent number 11,537,532
- Issue date Dec 27, 2022
- Texas Instmments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller with caching and non-caching modes
- Patent number 11,494,224
- Issue date Nov 8, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write control for read-modify-write operations in cache memory
- Patent number 11,487,616
- Issue date Nov 1, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 11,461,127
- Issue date Oct 4, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling non-correctable errors
- Patent number 11,416,334
- Issue date Aug 16, 2022
- Texas Instmments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aliased mode for cache controller
- Patent number 11,392,498
- Issue date Jul 19, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with wire reduction and physical congest...
- Patent number 11,321,268
- Issue date May 3, 2022
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-requestor memory access pipeline and arbiter
- Patent number 11,321,248
- Issue date May 3, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
WRITE STREAMING WITH CACHE WRITE ACKNOWLEDGMENT IN A PROCESSOR
- Publication number 20240168883
- Publication date May 23, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20240152385
- Publication date May 9, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20240095169
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20240045803
- Publication date Feb 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20240036867
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MERGING DATA FOR WRITE ALLOCATE
- Publication number 20240004694
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER
- Publication number 20240004793
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20230409376
- Publication date Dec 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
- Publication number 20230393933
- Publication date Dec 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE FOR MEMORY CONTROLLER
- Publication number 20230333982
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CACHE SECURITY
- Publication number 20230325314
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20230297469
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20230297506
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20230251975
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
- Publication number 20230254907
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION
- Publication number 20230244611
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20230185719
- Publication date Jun 15, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
- Publication number 20230176975
- Publication date Jun 8, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20230058689
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20230023242
- Publication date Jan 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
- Publication number 20230013270
- Publication date Jan 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING NON-CORRECTABLE ERRORS
- Publication number 20220391283
- Publication date Dec 8, 2022
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIASED MODE FOR CACHE CONTROLLER
- Publication number 20220327055
- Publication date Oct 13, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...
- Publication number 20220261373
- Publication date Aug 18, 2022
- TEXAS INSTRUMENTS INCORPORATED
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-REQUESTOR MEMORY ACCESS PIPELINE AND ARBITER
- Publication number 20220261360
- Publication date Aug 18, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20220253382
- Publication date Aug 11, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Preload Operations Using Streaming Engine
- Publication number 20220244957
- Publication date Aug 4, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20220245069
- Publication date Aug 4, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20220237122
- Publication date Jul 28, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20220229690
- Publication date Jul 21, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING

Abhijeet A. Chachad

Person

Patents Grantslast 30 patents

Write control for read-modify-write operations in cache memory

Multiple-requestor memory access pipeline and arbiter

Prefetch kill and revival in an instruction cache

Memory pipeline control in a hierarchical memory system

Write streaming with cache write acknowledgment in a processor

Controller with caching and non-caching modes

Cache size change

Multicore bus architecture with wire reduction and physical congest...

Hardware coherence signaling protocol

Implied fence on stream open

Error correcting codes for multi-master memory controller

Merging data for write allocate

Global coherence operations

Multi-level cache security

Shadow caches for level 2 cache controller

Hardware coherence for memory controller

Parallelized scrubbing transactions

Cache coherence shared state suppression

Prefetch kill and revival in an instruction cache

Pipelined read-modify-write operations in cache memory

Memory pipeline control in a hierarchical memory system

Prefetch management in a hierarchical cache system

Lookahead priority collection to support priority elevation

Controller with caching and non-caching modes

Write control for read-modify-write operations in cache memory

Pipeline arbitration

Handling non-correctable errors

Aliased mode for cache controller

Multicore bus architecture with wire reduction and physical congest...

Multiple-requestor memory access pipeline and arbiter

Patents Applicationslast 30 patents

WRITE STREAMING WITH CACHE WRITE ACKNOWLEDGMENT IN A PROCESSOR

CONTROLLER WITH CACHING AND NON-CACHING MODES

CACHE SIZE CHANGE

HARDWARE COHERENCE SIGNALING PROTOCOL

IMPLIED FENCE ON STREAM OPEN

MERGING DATA FOR WRITE ALLOCATE

SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER

GLOBAL COHERENCE OPERATIONS

ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER

HARDWARE COHERENCE FOR MEMORY CONTROLLER

MULTI-LEVEL CACHE SECURITY

PARALLELIZED SCRUBBING TRANSACTIONS

CACHE COHERENCE SHARED STATE SUPPRESSION

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM

CONTROLLER WITH CACHING AND NON-CACHING MODES

PIPELINE ARBITRATION

WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY

HANDLING NON-CORRECTABLE ERRORS

ALIASED MODE FOR CACHE CONTROLLER

MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...

MULTIPLE-REQUESTOR MEMORY ACCESS PIPELINE AND ARBITER

CACHE SIZE CHANGE

Cache Preload Operations Using Streaming Engine

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

GLOBAL COHERENCE OPERATIONS