Abhijit Jayant Pethe

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device having doped epitaxial region and its methods...
- Patent number 11,908,934
- Issue date Feb 20, 2024
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 11,869,939
- Issue date Jan 9, 2024
- Sony Group Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 11,302,777
- Issue date Apr 12, 2022
- Sony Group Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate contact structure over active gate and method to fabricate same
- Patent number 11,004,739
- Issue date May 11, 2021
- Intel Corporation
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having doped epitaxial region and its methods...
- Patent number 10,957,796
- Issue date Mar 23, 2021
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around (GAA) transistors with nanowires on an isolation pe...
- Patent number 10,847,631
- Issue date Nov 24, 2020
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,804,357
- Issue date Oct 13, 2020
- Sony Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,580,860
- Issue date Mar 3, 2020
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,283,589
- Issue date May 7, 2019
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate-all-around (GAA) transistor with stacked nanowires on locally...
- Patent number 10,229,981
- Issue date Mar 12, 2019
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate contact structure over active gate and method to fabricate same
- Patent number 10,192,783
- Issue date Jan 29, 2019
- Intel Corporation
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,121,856
- Issue date Nov 6, 2018
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 9,859,368
- Issue date Jan 2, 2018
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Methods for fabricating strained gate-all-around semiconductor devi...
- Patent number 9,484,272
- Issue date Nov 1, 2016
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 9,484,447
- Issue date Nov 1, 2016
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Three-dimensional germanium-based semiconductor devices formed on g...
- Patent number 9,472,399
- Issue date Oct 18, 2016
- Intel Corporation
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact structure over active gate and method to fabricate same
- Patent number 9,461,143
- Issue date Oct 4, 2016
- Intel Corporation
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional germanium-based semiconductor devices formed on g...
- Patent number 9,041,106
- Issue date May 26, 2015
- Intel Corporation
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained gate-all-around semiconductor devices formed on globally o...
- Patent number 8,735,869
- Issue date May 27, 2014
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Semiconductor device having doped epitaxial region and its methods...
- Patent number 8,598,003
- Issue date Dec 3, 2013
- Intel Corporation
- Anand S. Murtthy
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20240153995
- Publication date May 9, 2024
- SONY GROUP CORPORATION
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...
- Publication number 20240145592
- Publication date May 2, 2024
- Intel Corporation
- Anand S. MURTHY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20220262901
- Publication date Aug 18, 2022
- SONY GROUP CORPORATION
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME
- Publication number 20210210385
- Publication date Jul 8, 2021
- Intel Corporation
- Abhijit Jayant PETHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...
- Publication number 20210159339
- Publication date May 27, 2021
- Intel Corporation
- Anand S. MURTHY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20210050418
- Publication date Feb 18, 2021
- Sony Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20200152738
- Publication date May 14, 2020
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20190214461
- Publication date Jul 11, 2019
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...
- Publication number 20190157411
- Publication date May 23, 2019
- Intel Corporation
- Annalisa CAPPELLANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME
- Publication number 20190115257
- Publication date Apr 18, 2019
- Intel Corporation
- Abhijit Jayant PETHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20190051725
- Publication date Feb 14, 2019
- Intel Corporation
- Seiyon KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20180122901
- Publication date May 3, 2018
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20170047400
- Publication date Feb 16, 2017
- Intel Corporation
- Seiyon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...
- Publication number 20170047416
- Publication date Feb 16, 2017
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20170025499
- Publication date Jan 26, 2017
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME
- Publication number 20170004998
- Publication date Jan 5, 2017
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Fabricating Strained Gate-All-Around Semiconductor Devi...
- Publication number 20160284605
- Publication date Sep 29, 2016
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...
- Publication number 20150318219
- Publication date Nov 5, 2015
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20150255280
- Publication date Sep 10, 2015
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...
- Publication number 20140084342
- Publication date Mar 27, 2014
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20140084370
- Publication date Mar 27, 2014
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...
- Publication number 20140084369
- Publication date Mar 27, 2014
- ANAND S. MURTHY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME
- Publication number 20140077305
- Publication date Mar 20, 2014
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20140001441
- Publication date Jan 2, 2014
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Application
AREA SCALING ON TRIGATE TRANSISTORS
- Publication number 20130320453
- Publication date Dec 5, 2013
- Abhijit Jayant Pethe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...
- Publication number 20110147828
- Publication date Jun 23, 2011
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS

Abhijit Jayant Pethe

Person

Patents Grantslast 30 patents

Semiconductor device having doped epitaxial region and its methods...

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Gate contact structure over active gate and method to fabricate same

Semiconductor device having doped epitaxial region and its methods...

Gate-all-around (GAA) transistors with nanowires on an isolation pe...

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Gate-all-around (GAA) transistor with stacked nanowires on locally...

Gate contact structure over active gate and method to fabricate same

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Methods for fabricating strained gate-all-around semiconductor devi...

Integration methods to fabricate internal spacers for nanowire devices

Three-dimensional germanium-based semiconductor devices formed on g...

Gate contact structure over active gate and method to fabricate same

Three-dimensional germanium-based semiconductor devices formed on g...

Strained gate-all-around semiconductor devices formed on globally o...

Semiconductor device having doped epitaxial region and its methods...

Patents Applicationslast 30 patents

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

Methods for Fabricating Strained Gate-All-Around Semiconductor Devi...

STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY O...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

AREA SCALING ON TRIGATE TRANSISTORS

SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS...