Abhijith Arakali

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Karnataka, IN

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Patents Grantslast 30 patents

Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 9,065,430
- Issue date Jun 23, 2015
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 8,704,550
- Issue date Apr 22, 2014
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Comparator with reduced power consumption
- Patent number 7,830,183
- Issue date Nov 9, 2010
- Texas Instruments Incorporated
- Sumantra Seth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Biasing scheme for low-voltage MOS cascode current mirrors
- Patent number 7,639,081
- Issue date Dec 29, 2009
- Texas Instuments Incorporated
- Abhijith Arakali
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20140247071
- Publication date Sep 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPARATOR WITH REDUCED POWER CONSUMPTION
- Publication number 20100148854
- Publication date Jun 17, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Sumantra Seth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20090140772
- Publication date Jun 4, 2009
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Biasing Scheme for Low-Voltage MOS Cascode Current Mirrors
- Publication number 20080186101
- Publication date Aug 7, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Abhijith Arakali
- G05 - CONTROLLING REGULATING