Abhishek Ghosh

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
True single-phase clock (TSPC) NAND-based reset flip-flop
- Patent number 11,569,799
- Issue date Jan 31, 2023
- Samsung Electronics Co., Ltd.
- Aroma Bhat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pre-discharging based flip-flop with a negative setup time
- Patent number 11,362,648
- Issue date Jun 14, 2022
- Samsung Electronics Co., Ltd.
- Aroma Bhat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three-input exclusive NOR/OR gate using a CMOS circuit
- Patent number 11,152,942
- Issue date Oct 19, 2021
- Samsung Electronics Co., Ltd.
- Hareharan Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip flop circuit
- Patent number 10,812,055
- Issue date Oct 20, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Excess loop delay estimation and correction
- Patent number 10,727,861
- Issue date Jul 28, 2020
- MaxLinear, Inc.
- Chandrajit Debnath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-flop with single pre-charge node
- Patent number 10,715,118
- Issue date Jul 14, 2020
- Samsung Electronics Co., Ltd.
- Shyam Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Area and power efficient circuits for high-density standard cell li...
- Patent number 10,672,756
- Issue date Jun 2, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low voltage tolerant ultra-low power edge triggered flip-flop for s...
- Patent number 10,651,850
- Issue date May 12, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-linearity flash analog to digital converter
- Patent number 10,615,815
- Issue date Apr 7, 2020
- MaxLinear, Inc.
- Rishi Mathur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sense amplifier flip-flop and method for fixing setup time violatio...
- Patent number 10,566,959
- Issue date Feb 18, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking scheme in nonlinear systems for distortion improvement
- Patent number 10,187,017
- Issue date Jan 22, 2019
- MaxLinear, Inc.
- Prasun Kali Bhattacharyya
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
- Publication number 20240339992
- Publication date Oct 10, 2024
- Samsung Electronics Co., Ltd.
- Mitesh GOYAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS
- Publication number 20240311082
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Saurabh Shankar ZOND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR SOURCE MEASUREMENT UNIT (SMU) OPERATION
- Publication number 20240310411
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Rajavelu Thinakaran
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF OPTIMIZING AREA FOR LOGIC CELLS AND OPTIMIZED LOGIC CELLS
- Publication number 20240232496
- Publication date Jul 11, 2024
- Samsung Electronics Co., Ltd.
- ABDUR RAKHEEB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC CMOS-BASED FULL ADDER CIRCUITS
- Publication number 20230418556
- Publication date Dec 28, 2023
- Samsung Electronics Co., Ltd.
- Debojyoti Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRUE SINGLE-PHASE CLOCK (TSPC) NAND-BASED RESET FLIP-FLOP
- Publication number 20220173725
- Publication date Jun 2, 2022
- Samsung Electronics Co., Ltd.
- AROMA BHAT
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PRE-DISCHARGING BASED FLIP-FLOP WITH A NEGATIVE SETUP TIME
- Publication number 20210184660
- Publication date Jun 17, 2021
- Samsung Electronics Co., Ltd.
- Aroma Bhat
- G01 - MEASURING TESTING
Information Patent Application
THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT
- Publication number 20210167781
- Publication date Jun 3, 2021
- Samsung Electronics Co., Ltd.
- Hareharan Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA AND POWER EFFICIENT CIRCUITS FOR HIGH-DENSITY STANDARD CELL LI...
- Publication number 20200266185
- Publication date Aug 20, 2020
- Samsung Electronics Co., Ltd.
- Sajal MITTAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA AND POWER EFFICIENT CIRCUITS FOR HIGH-DENSITY STANDARD CELL LI...
- Publication number 20200144245
- Publication date May 7, 2020
- Samsung Electronics Co., Ltd.
- Sajal MITTAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLIP FLOP
- Publication number 20200136594
- Publication date Apr 30, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW VOLTAGE TOLERANT ULTRA-LOW POWER EDGE TRIGGERED FLIP-FLOP FOR S...
- Publication number 20200067507
- Publication date Feb 27, 2020
- Samsung Electronics Co., Ltd.
- Sajal Mittal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
D FLIP-FLOPS WITH LOW CLOCK DISSIPATION POWER
- Publication number 20200044631
- Publication date Feb 6, 2020
- Samsung Electronics Co., Ltd.
- Shyam AGARWAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCKING SCHEME IN NONLINEAR SYSTEMS FOR DISTORTION IMPROVEMENT
- Publication number 20200021250
- Publication date Jan 16, 2020
- MaxLinear, Inc.
- Prasun Kali Bhattacharyya
- G11 - INFORMATION STORAGE
Information Patent Application
EXCESS LOOP DELAY ESTIMATION AND CORRECTION
- Publication number 20190379390
- Publication date Dec 12, 2019
- MaxLinear, Inc.
- Chandrajit Debnath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-Linearity Flash Analog to Digital Converter
- Publication number 20190341926
- Publication date Nov 7, 2019
- Maxlinear, Inc.
- Rishi Mathur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP WITH SINGLE PRE-CHARGE NODE
- Publication number 20190058461
- Publication date Feb 21, 2019
- Samsung Electronics Co., Ltd.
- Shyam AGARWAL
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCKING SCHEME IN NONLINEAR SYSTEMS FOR DISTORTION IMPROVEMENT
- Publication number 20180198419
- Publication date Jul 12, 2018
- MaxLinear, Inc.
- Prasun Kali Bhattacharyya
- H03 - BASIC ELECTRONIC CIRCUITRY

Abhishek Ghosh

Person

Patents Grantslast 30 patents

True single-phase clock (TSPC) NAND-based reset flip-flop

Pre-discharging based flip-flop with a negative setup time

Three-input exclusive NOR/OR gate using a CMOS circuit

Flip flop circuit

Excess loop delay estimation and correction

Flip-flop with single pre-charge node

Area and power efficient circuits for high-density standard cell li...

Low voltage tolerant ultra-low power edge triggered flip-flop for s...

High-linearity flash analog to digital converter

Sense amplifier flip-flop and method for fixing setup time violatio...

Clocking scheme in nonlinear systems for distortion improvement

Patents Applicationslast 30 patents

LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY

STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

METHODS AND APPARATUS FOR SOURCE MEASUREMENT UNIT (SMU) OPERATION

METHOD OF OPTIMIZING AREA FOR LOGIC CELLS AND OPTIMIZED LOGIC CELLS

STATIC CMOS-BASED FULL ADDER CIRCUITS

TRUE SINGLE-PHASE CLOCK (TSPC) NAND-BASED RESET FLIP-FLOP

PRE-DISCHARGING BASED FLIP-FLOP WITH A NEGATIVE SETUP TIME

THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT

AREA AND POWER EFFICIENT CIRCUITS FOR HIGH-DENSITY STANDARD CELL LI...

AREA AND POWER EFFICIENT CIRCUITS FOR HIGH-DENSITY STANDARD CELL LI...

FLIP FLOP

LOW VOLTAGE TOLERANT ULTRA-LOW POWER EDGE TRIGGERED FLIP-FLOP FOR S...

D FLIP-FLOPS WITH LOW CLOCK DISSIPATION POWER

CLOCKING SCHEME IN NONLINEAR SYSTEMS FOR DISTORTION IMPROVEMENT

EXCESS LOOP DELAY ESTIMATION AND CORRECTION

High-Linearity Flash Analog to Digital Converter

FLIP-FLOP WITH SINGLE PRE-CHARGE NODE

CLOCKING SCHEME IN NONLINEAR SYSTEMS FOR DISTORTION IMPROVEMENT