ABHISHEK VENKATESH

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Controlling coarse pixel size from a stencil buffer
- Patent number 12,243,125
- Issue date Mar 4, 2025
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute optimization mechanism for deep neural networks
- Patent number 12,086,705
- Issue date Sep 10, 2024
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synergistic temporal anti-aliasing and coarse pixel shading technology
- Patent number 11,871,142
- Issue date Jan 9, 2024
- Intel Corporation
- Travis T. Schluessler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Controlling coarse pixel size from a stencil buffer
- Patent number 11,869,119
- Issue date Jan 9, 2024
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid low power homogenous grapics processing units
- Patent number 11,762,696
- Issue date Sep 19, 2023
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leveraging control surface fast clears to optimize 3D operations
- Patent number 11,763,515
- Issue date Sep 19, 2023
- Intel Corporation
- Devan Burke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Light field displays having synergistic data formatting, re-project...
- Patent number 11,688,366
- Issue date Jun 27, 2023
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anti-aliasing adaptive shader with pixel tile coverage raster rule...
- Patent number 11,663,774
- Issue date May 30, 2023
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mutli-frame renderer
- Patent number 11,636,567
- Issue date Apr 25, 2023
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 11,494,867
- Issue date Nov 8, 2022
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Positional only shading pipeline (POSH) geometry data processing wi...
- Patent number 11,461,959
- Issue date Oct 4, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anti-aliasing adaptive shader with pixel tile coverage raster rule...
- Patent number 11,302,066
- Issue date Apr 12, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequent data value compression for graphics processing units
- Patent number 11,263,720
- Issue date Mar 1, 2022
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
GPU mixed primitive topology type processing
- Patent number 11,257,182
- Issue date Feb 22, 2022
- Intel Corporation
- John Gierach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synergistic temporal anti-aliasing and coarse pixel shading technology
- Patent number 11,252,370
- Issue date Feb 15, 2022
- Intel Corporation
- Travis T. Schluessler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Controlling coarse pixel size from a stencil buffer
- Patent number 11,244,479
- Issue date Feb 8, 2022
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid low power homogenous grapics processing units
- Patent number 11,169,850
- Issue date Nov 9, 2021
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mutli-frame renderer
- Patent number 11,132,759
- Issue date Sep 28, 2021
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Light field displays having synergistic data formatting, re-project...
- Patent number 11,107,444
- Issue date Aug 31, 2021
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile-based immediate mode rendering with early hierarchical-z
- Patent number 11,062,506
- Issue date Jul 13, 2021
- Intel Corporation
- Andrew T. Lauritzen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended local memory including compressed on-chip vertex data
- Patent number 11,030,713
- Issue date Jun 8, 2021
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leveraging control surface fast clears to optimize 3D operations
- Patent number 10,964,087
- Issue date Mar 30, 2021
- Intel Corporation
- Devan Burke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile-based multiple resolution rendering of images
- Patent number 10,937,126
- Issue date Mar 2, 2021
- Intel Corporation
- John Gierach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional shader for graphics
- Patent number 10,930,060
- Issue date Feb 23, 2021
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-resolution image plane rendering within an improved graphics...
- Patent number 10,867,427
- Issue date Dec 15, 2020
- Intel Corporation
- Michael Apodaca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 10,861,126
- Issue date Dec 8, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anti-aliasing adaptive shader with pixel tile coverage raster rule...
- Patent number 10,803,656
- Issue date Oct 13, 2020
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Facilitating dynamic runtime transformation of graphics processing...
- Patent number 10,796,397
- Issue date Oct 6, 2020
- Intel Corporation
- James A. Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor with tiled compute kernels
- Patent number 10,783,603
- Issue date Sep 22, 2020
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequent data value compression for graphics processing units
- Patent number 10,748,238
- Issue date Aug 18, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
- Publication number 20250053797
- Publication date Feb 13, 2025
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER
- Publication number 20240161356
- Publication date May 16, 2024
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20240004713
- Publication date Jan 4, 2024
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...
- Publication number 20220301259
- Publication date Sep 22, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER
- Publication number 20220262047
- Publication date Aug 18, 2022
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20220206853
- Publication date Jun 30, 2022
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY
- Publication number 20220182575
- Publication date Jun 9, 2022
- Intel Corporation
- Travis T. Schluessler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MUTLI-FRAME RENDERER
- Publication number 20220172316
- Publication date Jun 2, 2022
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIGHT FIELD DISPLAYS HAVING SYNERGISTIC DATA FORMATTING, RE-PROJECT...
- Publication number 20220059054
- Publication date Feb 24, 2022
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING CONTROL SURFACE FAST CLEARS TO OPTIMIZE 3D OPERATIONS
- Publication number 20210287420
- Publication date Sep 16, 2021
- Intel Corporation
- Devan Burke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20210256653
- Publication date Aug 19, 2021
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...
- Publication number 20210097756
- Publication date Apr 1, 2021
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequent Data Value Compression for Graphics Processing Units
- Publication number 20210035257
- Publication date Feb 4, 2021
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY
- Publication number 20210014450
- Publication date Jan 14, 2021
- Intel Corporation
- Travis T. Schluessler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
- Publication number 20210012452
- Publication date Jan 14, 2021
- Intel Corporation
- John Gierach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER
- Publication number 20200402270
- Publication date Dec 24, 2020
- Intel Corporation
- Karthik Vaidyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE-BASED IMMEDIATE MODE RENDERING WITH EARLY HIERARCHICAL-Z
- Publication number 20200402298
- Publication date Dec 24, 2020
- Intel Corporation
- Andrew T. Lauritzen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20200402196
- Publication date Dec 24, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WI...
- Publication number 20200334896
- Publication date Oct 22, 2020
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20200210238
- Publication date Jul 2, 2020
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIGHT FIELD DISPLAYS HAVING SYNERGISTIC DATA FORMATTING, RE-PROJECT...
- Publication number 20200211511
- Publication date Jul 2, 2020
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-RESOLUTION IMAGE PLANE RENDERING WITHIN AN IMPROVED GRAPHICS...
- Publication number 20200074714
- Publication date Mar 5, 2020
- Intel Corporation
- Michael Apodaca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...
- Publication number 20200043224
- Publication date Feb 6, 2020
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING CONTROL SURFACE FAST CLEARS TO OPTIMIZE 3D OPERATIONS
- Publication number 20190378322
- Publication date Dec 12, 2019
- Intel Corporation
- Devan Burke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
- Publication number 20190355084
- Publication date Nov 21, 2019
- Intel Corporation
- John Gierach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE-BASED MULTIPLE RESOLUTION RENDERING OF IMAGES
- Publication number 20190355091
- Publication date Nov 21, 2019
- Intel Corporation
- John Gierach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequent Data Value Compression for Graphics Processing Units
- Publication number 20190272613
- Publication date Sep 5, 2019
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Instruction Latency Management in SIMD Machines
- Publication number 20190266069
- Publication date Aug 29, 2019
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MUTLI-FRAME RENDERER
- Publication number 20190259127
- Publication date Aug 22, 2019
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR WITH TILED COMPUTE KERNELS
- Publication number 20190259128
- Publication date Aug 22, 2019
- Intel Corporation
- Abhishek Venkatesh
- G06 - COMPUTING CALCULATING COUNTING

ABHISHEK VENKATESH

Person

Patents Grantslast 30 patents

Controlling coarse pixel size from a stencil buffer

Compute optimization mechanism for deep neural networks

Synergistic temporal anti-aliasing and coarse pixel shading technology

Controlling coarse pixel size from a stencil buffer

Hybrid low power homogenous grapics processing units

Leveraging control surface fast clears to optimize 3D operations

Light field displays having synergistic data formatting, re-project...

Anti-aliasing adaptive shader with pixel tile coverage raster rule...

Mutli-frame renderer

Asynchronous execution mechanism

Positional only shading pipeline (POSH) geometry data processing wi...

Anti-aliasing adaptive shader with pixel tile coverage raster rule...

Frequent data value compression for graphics processing units

GPU mixed primitive topology type processing

Synergistic temporal anti-aliasing and coarse pixel shading technology

Controlling coarse pixel size from a stencil buffer

Hybrid low power homogenous grapics processing units

Mutli-frame renderer

Light field displays having synergistic data formatting, re-project...

Tile-based immediate mode rendering with early hierarchical-z

Extended local memory including compressed on-chip vertex data

Leveraging control surface fast clears to optimize 3D operations

Tile-based multiple resolution rendering of images

Conditional shader for graphics

Multi-resolution image plane rendering within an improved graphics...

Asynchronous execution mechanism

Anti-aliasing adaptive shader with pixel tile coverage raster rule...

Facilitating dynamic runtime transformation of graphics processing...

Graphics processor with tiled compute kernels

Frequent data value compression for graphics processing units

Patents Applicationslast 30 patents

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...

CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY

MUTLI-FRAME RENDERER

LIGHT FIELD DISPLAYS HAVING SYNERGISTIC DATA FORMATTING, RE-PROJECT...

LEVERAGING CONTROL SURFACE FAST CLEARS TO OPTIMIZE 3D OPERATIONS

ASYNCHRONOUS EXECUTION MECHANISM

ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...

Frequent Data Value Compression for Graphics Processing Units

SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY

GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING

CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER

TILE-BASED IMMEDIATE MODE RENDERING WITH EARLY HIERARCHICAL-Z

ASYNCHRONOUS EXECUTION MECHANISM

POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WI...

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

LIGHT FIELD DISPLAYS HAVING SYNERGISTIC DATA FORMATTING, RE-PROJECT...

MULTI-RESOLUTION IMAGE PLANE RENDERING WITHIN AN IMPROVED GRAPHICS...

ANTI-ALIASING ADAPTIVE SHADER WITH PIXEL TILE COVERAGE RASTER RULE...

LEVERAGING CONTROL SURFACE FAST CLEARS TO OPTIMIZE 3D OPERATIONS

GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING

TILE-BASED MULTIPLE RESOLUTION RENDERING OF IMAGES

Frequent Data Value Compression for Graphics Processing Units

Dynamic Instruction Latency Management in SIMD Machines

MUTLI-FRAME RENDERER

GRAPHICS PROCESSOR WITH TILED COMPUTE KERNELS