Adam G. Kimura

Person

Westerville, OH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of identifying vulnerable regions in an integrated circuit
- Patent number 12,298,343
- Issue date May 13, 2025
- Battelle Memorial Institute
- Adam Gakuto Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabricated layout correlation
- Patent number 12,260,160
- Issue date Mar 25, 2025
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovery of a hierarchical functional representation of an integrat...
- Patent number 12,229,482
- Issue date Feb 18, 2025
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabricated layout correlation
- Patent number 11,907,627
- Issue date Feb 20, 2024
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovery of a hierarchical functional representation of an integrat...
- Patent number 11,651,126
- Issue date May 16, 2023
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Behavioral design recovery from flattened netlist
- Patent number 11,010,519
- Issue date May 18, 2021
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DESIGN TO FABRICATED LAYOUT CORRELATION
- Publication number 20250209243
- Publication date Jun 26, 2025
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Identifying Vulnerable Regions in an Integrated Circuit
- Publication number 20250199061
- Publication date Jun 19, 2025
- Battelle Memorial Institute
- Adam Gakuto KIMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...
- Publication number 20250165686
- Publication date May 22, 2025
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN TO FABRICATED LAYOUT CORRELATION
- Publication number 20240249050
- Publication date Jul 25, 2024
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR VERIFICATION AND VALIDATION OF INTEGRATED CIR...
- Publication number 20240169512
- Publication date May 23, 2024
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-DESTRUCTIVE VERIFICATION OF INTEGRATED CIRCUITS
- Publication number 20230377127
- Publication date Nov 23, 2023
- Battelle Memorial Institute
- Thomas F. Kent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT EXTRACTION USING PARALLELIZED TILE IMAGE...
- Publication number 20230298159
- Publication date Sep 21, 2023
- Battelle Memorial Institute
- Adam R. Waite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...
- Publication number 20230289502
- Publication date Sep 14, 2023
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Identifying Vulnerable Regions in an Integrated Circuit
- Publication number 20230138247
- Publication date May 4, 2023
- Battelle Memorial Institute
- Adam Gakuto KIMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL CIRCUIT REPRESENTATION USING A SPATIALLY RESOLVED NETLIST
- Publication number 20230044517
- Publication date Feb 9, 2023
- Battelle Memorial Institute
- Timothy A. McDonley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED CIRCUIT DESIGN VALIDATION
- Publication number 20230017484
- Publication date Jan 19, 2023
- Battelle Memorial Institute
- Adam KIMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN TO FABRICATED LAYOUT CORRELATION
- Publication number 20220188491
- Publication date Jun 16, 2022
- Battelle Memorial Institute
- Adam Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...
- Publication number 20210240894
- Publication date Aug 5, 2021
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BEHAVIORAL DESIGN RECOVERY FROM FLATTENED NETLIST
- Publication number 20200387654
- Publication date Dec 10, 2020
- Battelle Memorial Institute
- Adam G. Kimura
- G06 - COMPUTING CALCULATING COUNTING

Adam G. Kimura

Person

Patents Grantslast 30 patents

Method of identifying vulnerable regions in an integrated circuit

Fabricated layout correlation

Recovery of a hierarchical functional representation of an integrat...

Fabricated layout correlation

Recovery of a hierarchical functional representation of an integrat...

Behavioral design recovery from flattened netlist

Patents Applicationslast 30 patents

DESIGN TO FABRICATED LAYOUT CORRELATION

Method of Identifying Vulnerable Regions in an Integrated Circuit

RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...

DESIGN TO FABRICATED LAYOUT CORRELATION

SYSTEM AND METHOD FOR VERIFICATION AND VALIDATION OF INTEGRATED CIR...

NON-DESTRUCTIVE VERIFICATION OF INTEGRATED CIRCUITS

INTEGRATED CIRCUIT LAYOUT EXTRACTION USING PARALLELIZED TILE IMAGE...

RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...

Method of Identifying Vulnerable Regions in an Integrated Circuit

DIGITAL CIRCUIT REPRESENTATION USING A SPATIALLY RESOLVED NETLIST

AUTOMATED CIRCUIT DESIGN VALIDATION

DESIGN TO FABRICATED LAYOUT CORRELATION

RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRAT...

BEHAVIORAL DESIGN RECOVERY FROM FLATTENED NETLIST