Adam P. Matheny

Person

Beacon, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cross-hierarchy antenna condition verification
- Patent number 11,941,340
- Issue date Mar 26, 2024
- International Business Machines Corporation
- Michael Alexander Bowen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise impact on function (NIOF) reduction for integrated circuit de...
- Patent number 11,875,099
- Issue date Jan 16, 2024
- International Business Machines Corporation
- Gerald L Strevig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation and selection of universally routable via mesh specifica...
- Patent number 11,341,311
- Issue date May 24, 2022
- International Business Machines Corporation
- Joseph Koone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise impact on function (NIOF) reduction for integrated circuit de...
- Patent number 11,176,301
- Issue date Nov 16, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Net routing for integrated circuit (IC) design
- Patent number 11,030,376
- Issue date Jun 8, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock gating latch placement
- Patent number 10,943,040
- Issue date Mar 9, 2021
- International Business Machines Corporation
- Jesse Surprise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic partition reporting for integrated circuit design
- Patent number 10,885,243
- Issue date Jan 5, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-bit latch optimization for integrated circuit (IC) design
- Patent number 10,878,152
- Issue date Dec 29, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic partition identifiers for integrated circuit design
- Patent number 10,831,953
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-fanout latch placement optimization for integrated circuit (I...
- Patent number 10,831,966
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel power down processing of integrated circuit design
- Patent number 10,831,938
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for improving capacitance extraction performance by approxim...
- Patent number 10,360,338
- Issue date Jul 23, 2019
- International Business Machines Corporation
- Susan E. Cellier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for improving capacitance extraction performance
- Patent number 10,354,041
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource aware method for optimizing wires for slew, slack, or noise
- Patent number 10,331,840
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Alice H. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and computer program products for via capacitance extraction
- Patent number 10,169,516
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Susan E. Cellier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental parasitic extraction for coupled timing and power optim...
- Patent number 10,169,526
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation of modifications to microprocessor design
- Patent number 9,934,341
- Issue date Apr 3, 2018
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation of modifications to microprocessor design
- Patent number 9,928,322
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for improving capacitance extraction performance
- Patent number 9,886,541
- Issue date Feb 6, 2018
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental parasitic extraction for coupled timing and power optim...
- Patent number 9,858,383
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel incremental global routing
- Patent number 9,785,735
- Issue date Oct 10, 2017
- International Business Machines Corporation
- Paul M. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing repeater power
- Patent number 9,256,705
- Issue date Feb 9, 2016
- GLOBALFOUNDRIES Inc.
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing repeater power
- Patent number 9,223,918
- Issue date Dec 29, 2015
- GLOBALFOUNDRIES Inc.
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for an integrated circuit design for reducing coupling be...
- Patent number 8,032,851
- Issue date Oct 4, 2011
- International Business Machines Corporation
- Moussadek Belaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing coupling between wires of an electronic circuit
- Patent number 8,006,208
- Issue date Aug 23, 2011
- International Business Machines Corporation
- Moussadek Belaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and computer program product for coupled noise timi...
- Patent number 7,904,861
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Markus Buehler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sign-off timing closure of a VLSI chip
- Patent number 7,581,201
- Issue date Aug 25, 2009
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing wiring congestion in a VLSI chip design
- Patent number 6,958,545
- Issue date Oct 25, 2005
- International Business Machines Corporation
- Pooja M. Kotecha
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CROSS-HIERARCHY ANTENNA CONDITION VERIFICATION
- Publication number 20230051392
- Publication date Feb 16, 2023
- International Business Machines Corporation
- Michael Alexander Bowen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...
- Publication number 20230038399
- Publication date Feb 9, 2023
- International Business Machines Corporation
- Gerald L. Strevig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATING LATCH PLACEMENT
- Publication number 20210073344
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jesse SURPRISE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN
- Publication number 20210073347
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...
- Publication number 20210073346
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC UPDATE OF MACRO TIMING MODELS DURING HIGHER-LEVEL TIMING AN...
- Publication number 20190362043
- Publication date Nov 28, 2019
- International Business Machines Corporation
- Hemlata Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE
- Publication number 20180082009
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...
- Publication number 20180068052
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOURCE AWARE METHOD FOR OPTIMIZING WIRES FOR SLEW, SLACK, OR NOISE
- Publication number 20170206286
- Publication date Jul 20, 2017
- International Business Machines Corporation
- Alice H. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE BY APPROXIM...
- Publication number 20170206299
- Publication date Jul 20, 2017
- International Business Machines Corporation
- SUSAN E. CELLIER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...
- Publication number 20170177784
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND COMPUTER PROGRAM PRODUCTS FOR VIA CAPACITANCE EXTRACTION
- Publication number 20170169151
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Susan E. Cellier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE
- Publication number 20170161422
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN
- Publication number 20170132341
- Publication date May 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN
- Publication number 20170132340
- Publication date May 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING REPEATER POWER
- Publication number 20140088948
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING REPEATER POWER
- Publication number 20130275110
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
- Publication number 20100223588
- Publication date Sep 2, 2010
- International Business Machines Corporation
- Moussadek Belaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR COUPLED NOISE TIMI...
- Publication number 20080313588
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Markus Buehler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP
- Publication number 20080209376
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN...
- Publication number 20080184186
- Publication date Jul 31, 2008
- Moussadek Belaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING METHOD FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC...
- Publication number 20080148213
- Publication date Jun 19, 2008
- Moussadek Belaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for reducing wiring congestion in a VLSI chip design
- Publication number 20050151258
- Publication date Jul 14, 2005
- Pooja M. Kotecha
- G06 - COMPUTING CALCULATING COUNTING

Adam P. Matheny

Person

Patents Grantslast 30 patents

Cross-hierarchy antenna condition verification

Noise impact on function (NIOF) reduction for integrated circuit de...

Generation and selection of universally routable via mesh specifica...

Noise impact on function (NIOF) reduction for integrated circuit de...

Net routing for integrated circuit (IC) design

Clock gating latch placement

Logic partition reporting for integrated circuit design

Single-bit latch optimization for integrated circuit (IC) design

Logic partition identifiers for integrated circuit design

Multi-fanout latch placement optimization for integrated circuit (I...

Parallel power down processing of integrated circuit design

Method for improving capacitance extraction performance by approxim...

Process for improving capacitance extraction performance

Resource aware method for optimizing wires for slew, slack, or noise

Methods and computer program products for via capacitance extraction

Incremental parasitic extraction for coupled timing and power optim...

Simulation of modifications to microprocessor design

Simulation of modifications to microprocessor design

Process for improving capacitance extraction performance

Incremental parasitic extraction for coupled timing and power optim...

Parallel incremental global routing

Reducing repeater power

Reducing repeater power

Structure for an integrated circuit design for reducing coupling be...

Reducing coupling between wires of an electronic circuit

Method, system, and computer program product for coupled noise timi...

System and method for sign-off timing closure of a VLSI chip

Method for reducing wiring congestion in a VLSI chip design

Patents Applicationslast 30 patents

CROSS-HIERARCHY ANTENNA CONDITION VERIFICATION

NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...

CLOCK GATING LATCH PLACEMENT

NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN

NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...

DYNAMIC UPDATE OF MACRO TIMING MODELS DURING HIGHER-LEVEL TIMING AN...

PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE

INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...

RESOURCE AWARE METHOD FOR OPTIMIZING WIRES FOR SLEW, SLACK, OR NOISE

METHOD FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE BY APPROXIM...

INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...

METHODS AND COMPUTER PROGRAM PRODUCTS FOR VIA CAPACITANCE EXTRACTION

PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE

SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN

SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN

REDUCING REPEATER POWER

REDUCING REPEATER POWER

REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR COUPLED NOISE TIMI...

SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP

INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN...

ROUTING METHOD FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC...

Method for reducing wiring congestion in a VLSI chip design