Adarsh Chauhan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction and micro-architecture support for decompression on core
- Patent number 12,182,018
- Issue date Dec 31, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application programming interface for fine grained low latency deco...
- Patent number 12,028,094
- Issue date Jul 2, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 11,656,971
- Issue date May 23, 2023
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting a dynamic control flow re-convergence point for condition...
- Patent number 11,645,078
- Issue date May 9, 2023
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 11,256,599
- Issue date Feb 22, 2022
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 10,915,421
- Issue date Feb 9, 2021
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic predication of hard-to-predict convergent branches
- Patent number 10,754,655
- Issue date Aug 25, 2020
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Technology For Dynamically Tuning Processor Features
- Publication number 20220206925
- Publication date Jun 30, 2022
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...
- Publication number 20220197659
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES
- Publication number 20220197643
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Micro-Architecture Support for Decompression on Core
- Publication number 20220197799
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...
- Publication number 20220197813
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technology For Dynamically Tuning Processor Features
- Publication number 20210109839
- Publication date Apr 15, 2021
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTING A DYNAMIC CONTROL FLOW RE-CONVERGENCE POINT FOR CONDITION...
- Publication number 20210019149
- Publication date Jan 21, 2021
- Intel Corporation
- ADARSH CHAUHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES
- Publication number 20200004542
- Publication date Jan 2, 2020
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING

Adarsh Chauhan

Person

Patents Grantslast 30 patents

Instruction and micro-architecture support for decompression on core

Application programming interface for fine grained low latency deco...

Technology for dynamically tuning processor features

Detecting a dynamic control flow re-convergence point for condition...

Technology for dynamically tuning processor features

Technology for dynamically tuning processor features

Automatic predication of hard-to-predict convergent branches

Patents Applicationslast 30 patents

Technology For Dynamically Tuning Processor Features

APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...

SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES

Instruction and Micro-Architecture Support for Decompression on Core

APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...

Technology For Dynamically Tuning Processor Features

DETECTING A DYNAMIC CONTROL FLOW RE-CONVERGENCE POINT FOR CONDITION...

AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES