Adarsh Panikkar

Person

Tacoma, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Training pattern for a biased clock recovery tracking loop
- Patent number 8,098,783
- Issue date Jan 17, 2012
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Non-integer word size translation through rotation of different buf...
- Patent number 7,672,335
- Issue date Mar 2, 2010
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual clock domain deskew circuit
- Patent number 7,656,983
- Issue date Feb 2, 2010
- Intel Corporation
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Training pattern based de-skew mechanism and frame alignment
- Patent number 7,500,131
- Issue date Mar 3, 2009
- Intel Corporation
- Adarsh Panikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Various methods and apparatuses for lane to lane deskewing
- Patent number 7,466,723
- Issue date Dec 16, 2008
- Intel Corporation
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training pattern for a biased clock recovery tracking loop
- Patent number 7,369,634
- Issue date May 6, 2008
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Delaying lanes in order to align all lanes crossing between two clo...
- Patent number 7,346,795
- Issue date Mar 18, 2008
- Intel Corporation
- Daniel S. Klowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interpolator testing system
- Patent number 7,043,392
- Issue date May 9, 2006
- Intel Corporation
- Kersi H. Vakil
- G11 - INFORMATION STORAGE
Information Patent Grant
Interpolator linearity testing system
- Patent number 7,009,431
- Issue date Mar 7, 2006
- Intel Corporation
- Adarsh Panikkar
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP
- Publication number 20080260082
- Publication date Oct 23, 2008
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Selective tracking of serial communication link data
- Publication number 20080130815
- Publication date Jun 5, 2008
- S. Reji Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual clock domain deskew circuit
- Publication number 20080080654
- Publication date Apr 3, 2008
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Keep-out asynchronous clock alignment scheme
- Publication number 20060146967
- Publication date Jul 6, 2006
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Keep-out clock alignment cycle coherency protection
- Publication number 20060149987
- Publication date Jul 6, 2006
- Daniel S. Klowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Training pattern for a biased clock recovery tracking loop
- Publication number 20060050822
- Publication date Mar 9, 2006
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Training pattern based de-skew mechanism and frame alignment
- Publication number 20060053328
- Publication date Mar 9, 2006
- Adarsh Panikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interpolator linearity testing system
- Publication number 20050285652
- Publication date Dec 29, 2005
- Adarsh Panikkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Various methods and apparatuses for lane to lane deskewing
- Publication number 20050286565
- Publication date Dec 29, 2005
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interpolator testing system
- Publication number 20050280452
- Publication date Dec 22, 2005
- Kersi H. Vakil
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Non-integer word size translation through rotation of different buf...
- Publication number 20050129070
- Publication date Jun 16, 2005
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Adarsh Panikkar

Person

Patents Grantslast 30 patents

Training pattern for a biased clock recovery tracking loop

Non-integer word size translation through rotation of different buf...

Dual clock domain deskew circuit

Training pattern based de-skew mechanism and frame alignment

Various methods and apparatuses for lane to lane deskewing

Training pattern for a biased clock recovery tracking loop

Delaying lanes in order to align all lanes crossing between two clo...

Interpolator testing system

Interpolator linearity testing system

Patents Applicationslast 30 patents

TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP

Selective tracking of serial communication link data

Dual clock domain deskew circuit

Keep-out asynchronous clock alignment scheme

Keep-out clock alignment cycle coherency protection

Training pattern for a biased clock recovery tracking loop

Training pattern based de-skew mechanism and frame alignment

Interpolator linearity testing system

Various methods and apparatuses for lane to lane deskewing

Interpolator testing system

Non-integer word size translation through rotation of different buf...