Agostino Pirovano

Person

Corbetta (MI), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Reading a multi-level memory cell
- Patent number 11,996,141
- Issue date May 28, 2024
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point array architecture for multiple decks
- Patent number 11,895,851
- Issue date Feb 6, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Segregation-based memory
- Patent number 11,869,585
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for programming a memory cell
- Patent number 11,817,148
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses including multi-level memory cells and methods of opera...
- Patent number 11,798,620
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level self-selecting memory device
- Patent number 11,769,551
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Three dimensional memory arrays
- Patent number 11,765,912
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Agostino Pirovano
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 11,763,886
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming enhancement in self-selecting memory
- Patent number 11,735,261
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Polarity-written cell architectures for a memory device
- Patent number 11,721,394
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Three dimensional memory arrays
- Patent number 11,696,454
- Issue date Jul 4, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with double protective liner
- Patent number 11,647,638
- Issue date May 9, 2023
- Intel Corporation
- Anna Maria Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional memory array
- Patent number 11,587,979
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Fabio Pellizzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory array
- Patent number 11,574,957
- Issue date Feb 7, 2023
- Micron Technology, Inc.
- Anna Maria Conti
- G11 - INFORMATION STORAGE
Information Patent Grant
Tapered memory cell profiles
- Patent number 11,545,625
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned memory decks in cross-point memory arrays
- Patent number 11,489,117
- Issue date Nov 1, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses including multi-level memory cells and methods of opera...
- Patent number 11,482,280
- Issue date Oct 25, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Material implication operations in memory
- Patent number 11,475,951
- Issue date Oct 18, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses including multi-level memory cells and methods of opera...
- Patent number 11,443,799
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for forming self-aligned memory structures
- Patent number 11,417,841
- Issue date Aug 16, 2022
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tapered cell profile and fabrication
- Patent number 11,404,637
- Issue date Aug 2, 2022
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory including a selector switch on a variable resistance memory...
- Patent number 11,404,479
- Issue date Aug 2, 2022
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-selecting memory array with horizontal access lines
- Patent number 11,404,117
- Issue date Aug 2, 2022
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells having resistors and formation of the same
- Patent number 11,374,059
- Issue date Jun 28, 2022
- Micron Technology, Inc.
- Fabio Pellizzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrays of memory cells and methods of forming an array of elevation...
- Patent number 11,302,748
- Issue date Apr 12, 2022
- Micron Technology, Inc.
- Anna Maria Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for programming a memory cell
- Patent number 11,302,393
- Issue date Apr 12, 2022
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading a multi-level memory cell
- Patent number 11,302,390
- Issue date Apr 12, 2022
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Drift mitigation with embedded refresh
- Patent number 11,217,322
- Issue date Jan 4, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming enhancement in self-selecting memory
- Patent number 11,200,950
- Issue date Dec 14, 2021
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Polarity-written cell architectures for a memory device
- Patent number 11,164,627
- Issue date Nov 2, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES
- Publication number 20230395113
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Giorgio Servalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE
- Publication number 20230260581
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL MEMORY ARCHITECTURE
- Publication number 20230262995
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS
- Publication number 20230114077
- Publication date Apr 13, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
- Publication number 20230027799
- Publication date Jan 26, 2023
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
- Publication number 20230005535
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERA...
- Publication number 20220366974
- Publication date Nov 17, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING
- Publication number 20220310195
- Publication date Sep 29, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
READING A MULTI-LEVEL MEMORY CELL
- Publication number 20220301619
- Publication date Sep 22, 2022
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR PROGRAMMING A MEMORY CELL
- Publication number 20220189551
- Publication date Jun 16, 2022
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORY
- Publication number 20220172779
- Publication date Jun 2, 2022
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Application
POLARITY-WRITTEN CELL ARCHITECTURES FOR A MEMORY DEVICE
- Publication number 20220122663
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
- Publication number 20220115068
- Publication date Apr 14, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES
- Publication number 20220059763
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LEVEL SELF-SELECTING MEMORY DEVICE
- Publication number 20220036946
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Andrea Redaelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
READING A MULTI-LEVEL MEMORY CELL
- Publication number 20220013167
- Publication date Jan 13, 2022
- Micron Technology, Inc.
- Mattia Robustelli
- G11 - INFORMATION STORAGE
Information Patent Application
SEGREGATION-BASED MEMORY
- Publication number 20210366541
- Publication date Nov 25, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS
- Publication number 20210328142
- Publication date Oct 21, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAY
- Publication number 20210273015
- Publication date Sep 2, 2021
- Micron Technology, Inc.
- Anna Maria Conti
- G11 - INFORMATION STORAGE
Information Patent Application
THREE DIMENSIONAL MEMORY ARRAYS
- Publication number 20210257408
- Publication date Aug 19, 2021
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY...
- Publication number 20210210552
- Publication date Jul 8, 2021
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Application
THREE DIMENSIONAL MEMORY ARRAYS
- Publication number 20210183947
- Publication date Jun 17, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TAPERED MEMORY CELL PROFILES
- Publication number 20210151673
- Publication date May 20, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MATERIAL IMPLICATION OPERATIONS IN MEMORY
- Publication number 20210151109
- Publication date May 20, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL MEMORY ARRAY
- Publication number 20210134885
- Publication date May 6, 2021
- Micron Technology, Inc.
- Fabio Pellizzer
- G11 - INFORMATION STORAGE
Information Patent Application
TAPERED CELL PROFILE AND FABRICATION
- Publication number 20210119123
- Publication date Apr 22, 2021
- Micron Technology, Inc.
- Andrea Redaelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
- Publication number 20210050521
- Publication date Feb 18, 2021
- Micron Technology, Inc.
- Stephen W. Russell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR PROGRAMMING A MEMORY CELL
- Publication number 20210005257
- Publication date Jan 7, 2021
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
MIXED CROSS POINT MEMORY
- Publication number 20200381046
- Publication date Dec 3, 2020
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Application
DRIFT MITIGATION WITH EMBEDDED REFRESH
- Publication number 20200372966
- Publication date Nov 26, 2020
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS

Agostino Pirovano

Person

Patents Grantslast 30 patents

Reading a multi-level memory cell

Cross point array architecture for multiple decks

Segregation-based memory

Techniques for programming a memory cell

Apparatuses including multi-level memory cells and methods of opera...

Multi-level self-selecting memory device

Three dimensional memory arrays

Techniques to access a self-selecting memory device

Programming enhancement in self-selecting memory

Polarity-written cell architectures for a memory device

Three dimensional memory arrays

Memory device with double protective liner

Three dimensional memory array

Three-dimensional memory array

Tapered memory cell profiles

Self-aligned memory decks in cross-point memory arrays

Apparatuses including multi-level memory cells and methods of opera...

Material implication operations in memory

Apparatuses including multi-level memory cells and methods of opera...

Techniques for forming self-aligned memory structures

Tapered cell profile and fabrication

Memory including a selector switch on a variable resistance memory...

Self-selecting memory array with horizontal access lines

Memory cells having resistors and formation of the same

Arrays of memory cells and methods of forming an array of elevation...

Techniques for programming a memory cell

Reading a multi-level memory cell

Drift mitigation with embedded refresh

Programming enhancement in self-selecting memory

Polarity-written cell architectures for a memory device

Patents Applicationslast 30 patents

TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES

TECHNIQUES FOR OPERATING A VERTICAL MEMORY ARCHITECTURE

VERTICAL MEMORY ARCHITECTURE

CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS

TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES

SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES

APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERA...

TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING

READING A MULTI-LEVEL MEMORY CELL

TECHNIQUES FOR PROGRAMMING A MEMORY CELL

PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORY

POLARITY-WRITTEN CELL ARCHITECTURES FOR A MEMORY DEVICE

TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

MULTI-LEVEL SELF-SELECTING MEMORY DEVICE

READING A MULTI-LEVEL MEMORY CELL

SEGREGATION-BASED MEMORY

SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS

THREE-DIMENSIONAL MEMORY ARRAY

THREE DIMENSIONAL MEMORY ARRAYS

MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY...

THREE DIMENSIONAL MEMORY ARRAYS

TAPERED MEMORY CELL PROFILES

MATERIAL IMPLICATION OPERATIONS IN MEMORY

THREE DIMENSIONAL MEMORY ARRAY

TAPERED CELL PROFILE AND FABRICATION

TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES

TECHNIQUES FOR PROGRAMMING A MEMORY CELL

MIXED CROSS POINT MEMORY

DRIFT MITIGATION WITH EMBEDDED REFRESH