Ahsanur Rahman

Person

Rancho Cordova, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-level memory cell sensing
- Patent number 7,551,489
- Issue date Jun 23, 2009
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with pseudo single bit memory cell and method
- Patent number 7,525,840
- Issue date Apr 28, 2009
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with pseudo single bit memory cell and method
- Patent number 7,272,041
- Issue date Sep 18, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT BITLINE STABILIZATION FOR PROGRAM INHIBIT IN NAND ARRAYS
- Publication number 20240136003
- Publication date Apr 25, 2024
- Intel NDTM US LLC
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
GROUPED GLOBAL WORDLINE DRIVER WITH SHARED BIAS SCHEME
- Publication number 20230082368
- Publication date Mar 16, 2023
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT BLOCK ARRAY FOR 3D NAND MEMORY
- Publication number 20220399057
- Publication date Dec 15, 2022
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERA...
- Publication number 20220172784
- Publication date Jun 2, 2022
- Intel Corporation
- Shantanu R. RAJWADE
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Array with Psedudo Single Bit Memory Cell and Method
- Publication number 20070268758
- Publication date Nov 22, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-level memory cell sensing
- Publication number 20070171708
- Publication date Jul 26, 2007
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array with pseudo single bit memory cell and method
- Publication number 20070002613
- Publication date Jan 4, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE

Ahsanur Rahman

Person

Patents Grantslast 30 patents

Multi-level memory cell sensing

Memory array with pseudo single bit memory cell and method

Memory array with pseudo single bit memory cell and method

Patents Applicationslast 30 patents

EFFICIENT BITLINE STABILIZATION FOR PROGRAM INHIBIT IN NAND ARRAYS

GROUPED GLOBAL WORDLINE DRIVER WITH SHARED BIAS SCHEME

SPLIT BLOCK ARRAY FOR 3D NAND MEMORY

MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERA...

Memory Array with Psedudo Single Bit Memory Cell and Method

Multi-level memory cell sensing

Memory array with pseudo single bit memory cell and method