Aiguo Lu

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and computer program for generating grounded shielding wires...
- Patent number 8,516,425
- Issue date Aug 20, 2013
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for balancing signal delay skew
- Patent number 8,239,813
- Issue date Aug 7, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay skew reduction system
- Patent number 7,996,804
- Issue date Aug 9, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing IC clock structures by minimizing clock uncertainty
- Patent number 7,356,785
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of buffer insertion to achieve pin specific delays
- Patent number 7,243,324
- Issue date Jul 10, 2007
- LSI Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing IC clock structures by minimizing clock uncertainty
- Patent number 7,096,442
- Issue date Aug 22, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of adder based circuit architecture
- Patent number 6,934,733
- Issue date Aug 23, 2005
- LSI Logic Corporation
- Sergej B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to find boolean function symmetries
- Patent number 6,868,536
- Issue date Mar 15, 2005
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process of restructuring logics in ICs for setup and hold time opti...
- Patent number 6,810,515
- Issue date Oct 26, 2004
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floor plan tester for integrated circuit design
- Patent number 6,701,493
- Issue date Mar 2, 2004
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of comparator architecture
- Patent number 6,691,283
- Issue date Feb 10, 2004
- LSI Logic Corporation
- Sergej B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assignment of cell coordinates
- Patent number 6,637,016
- Issue date Oct 21, 2003
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell placement in integrated circuit chips to remove cell overlap,...
- Patent number 6,629,304
- Issue date Sep 30, 2003
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist resynthesis program based on physical delay calculation
- Patent number 6,557,144
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing recomputation
- Patent number 6,553,551
- Issue date Apr 22, 2003
- LSI Logic Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Changing clock delays in an integrated circuit for skew optimization
- Patent number 6,550,045
- Issue date Apr 15, 2003
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method in integrating clock tree synthesis and timing optimization...
- Patent number 6,550,044
- Issue date Apr 15, 2003
- LSI Logic Corporation
- Ivan Pavisic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement-based integrated circuit re-synthesis tool using estimate...
- Patent number 6,546,541
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Dusan Petranovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution dependent clustering in buffer insertion of high fanou...
- Patent number 6,487,697
- Issue date Nov 26, 2002
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelization of resynthesis
- Patent number 6,470,487
- Issue date Oct 22, 2002
- LSI Logic Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC timing analysis with known false paths
- Patent number 6,463,572
- Issue date Oct 8, 2002
- LSI Logic Corporation
- Ivan Pavisic
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20120278783
- Publication date Nov 1, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20110258587
- Publication date Oct 20, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20090187873
- Publication date Jul 23, 2009
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing IC clock structures by minimizing clock uncertainty
- Publication number 20060190886
- Publication date Aug 24, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of buffer insertion to achieve pin specific delays
- Publication number 20060190901
- Publication date Aug 24, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing IC clock structures by minimizing clock uncertainty
- Publication number 20050010884
- Publication date Jan 13, 2005
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to find boolean function symmetries
- Publication number 20040098676
- Publication date May 20, 2004
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process of restructuring logics in ICs for setup and hold time opti...
- Publication number 20040060012
- Publication date Mar 25, 2004
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floor plan tester for integrated circuit design
- Publication number 20030188274
- Publication date Oct 2, 2003
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZATION OF RESYNTHESIS
- Publication number 20020162085
- Publication date Oct 31, 2002
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method and computer program for generating grounded shielding wires...

Method and apparatus for balancing signal delay skew

Signal delay skew reduction system

Optimizing IC clock structures by minimizing clock uncertainty

Method of buffer insertion to achieve pin specific delays

Optimizing IC clock structures by minimizing clock uncertainty

Optimization of adder based circuit architecture

Method to find boolean function symmetries

Process of restructuring logics in ICs for setup and hold time opti...

Floor plan tester for integrated circuit design

Optimization of comparator architecture

Assignment of cell coordinates

Cell placement in integrated circuit chips to remove cell overlap,...

Netlist resynthesis program based on physical delay calculation

Timing recomputation

Changing clock delays in an integrated circuit for skew optimization

Method in integrating clock tree synthesis and timing optimization...

Placement-based integrated circuit re-synthesis tool using estimate...

Distribution dependent clustering in buffer insertion of high fanou...

Parallelization of resynthesis

IC timing analysis with known false paths

Patents Applicationslast 30 patents

SIGNAL DELAY SKEW REDUCTION SYSTEM

SIGNAL DELAY SKEW REDUCTION SYSTEM

SIGNAL DELAY SKEW REDUCTION SYSTEM

Optimizing IC clock structures by minimizing clock uncertainty

Method of buffer insertion to achieve pin specific delays

Optimizing IC clock structures by minimizing clock uncertainty

Method to find boolean function symmetries

Process of restructuring logics in ICs for setup and hold time opti...

Floor plan tester for integrated circuit design

PARALLELIZATION OF RESYNTHESIS