Aiping Tan

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Die stack with reduced warpage
- Patent number 11,848,281
- Issue date Dec 19, 2023
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Grant
Interposer design in package structures for wire bonding applications
- Patent number 11,652,087
- Issue date May 16, 2023
- Tahoe Research, LTD.
- Aiping Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical bond-wire stacked chip-scale package with application-spec...
- Patent number 11,538,746
- Issue date Dec 27, 2022
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die stack with reduced warpage
- Patent number 11,081,451
- Issue date Aug 3, 2021
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stair-stacked dice device in a system in package, and methods of ma...
- Patent number 10,991,679
- Issue date Apr 27, 2021
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer design in package structures for wire bonding applications
- Patent number 10,971,478
- Issue date Apr 6, 2021
- Intel Corporation
- Aiping Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prepackaged stair-stacked memory module in a chip scale system in p...
- Patent number 10,930,622
- Issue date Feb 23, 2021
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Grant
Stair-stacked dice device in a system in package, and methods of ma...
- Patent number 10,770,434
- Issue date Sep 8, 2020
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prepackaged stair-stacked memory module in a chip scale system in p...
- Patent number 10,727,208
- Issue date Jul 28, 2020
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DIE STACK WITH REDUCED WARPAGE
- Publication number 20220020704
- Publication date Jan 20, 2022
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Application
INTERPOSER DESIGN IN PACKAGE STRUCTURES FOR WIRE BONDING APPLICATIONS
- Publication number 20210183819
- Publication date Jun 17, 2021
- Intel Corporation
- Aiping TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...
- Publication number 20200402961
- Publication date Dec 24, 2020
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...
- Publication number 20200357773
- Publication date Nov 12, 2020
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK WITH REDUCED WARPAGE
- Publication number 20200051929
- Publication date Feb 13, 2020
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DIE STACKS
- Publication number 20190371766
- Publication date Dec 5, 2019
- Intel Corporation
- Bin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER DESIGN IN PACKAGE STRUCTURES FOR WIRE BONDING APPLICATIONS
- Publication number 20190371767
- Publication date Dec 5, 2019
- Intel Corporation
- Aiping TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR WINDOWED SUBSTRATE INTEGRATED CIRCUIT PACKAGES
- Publication number 20190355700
- Publication date Nov 21, 2019
- Intel Corporation
- Aiping Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL BOND-WIRE STACKED CHIP-SCALE PACKAGE WITH APPLICATION-SPEC...
- Publication number 20190273037
- Publication date Sep 5, 2019
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...
- Publication number 20190229092
- Publication date Jul 25, 2019
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Application
STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...
- Publication number 20190214370
- Publication date Jul 11, 2019
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Die stack with reduced warpage

Interposer design in package structures for wire bonding applications

Vertical bond-wire stacked chip-scale package with application-spec...

Die stack with reduced warpage

Stair-stacked dice device in a system in package, and methods of ma...

Interposer design in package structures for wire bonding applications

Prepackaged stair-stacked memory module in a chip scale system in p...

Stair-stacked dice device in a system in package, and methods of ma...

Prepackaged stair-stacked memory module in a chip scale system in p...

Patents Applicationslast 30 patents

DIE STACK WITH REDUCED WARPAGE

INTERPOSER DESIGN IN PACKAGE STRUCTURES FOR WIRE BONDING APPLICATIONS

STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...

PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...

DIE STACK WITH REDUCED WARPAGE

INTEGRATED CIRCUIT DIE STACKS

INTERPOSER DESIGN IN PACKAGE STRUCTURES FOR WIRE BONDING APPLICATIONS

TECHNIQUES FOR WINDOWED SUBSTRATE INTEGRATED CIRCUIT PACKAGES

VERTICAL BOND-WIRE STACKED CHIP-SCALE PACKAGE WITH APPLICATION-SPEC...

PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...

STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...