Aj KleinOsowski

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for hardening latches in SOI CMOS devices
- Patent number 8,354,858
- Issue date Jan 15, 2013
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radiation tolerance by clock signal interleaving
- Patent number 8,271,912
- Issue date Sep 18, 2012
- International Business Machines Corporation
- Matthew R. Ellavsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carbon nanotube based integrated semiconductor circuit
- Patent number 8,211,741
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Joerg Appenzeller
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Carbon nanotube based integrated semiconductor circuit
- Patent number 8,017,934
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Joerg Appenzeller
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Apparatus and method for hardening latches in SOI CMOS devices
- Patent number 7,888,959
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for QCRIT measurement in bulk CMOS using a switched capacito...
- Patent number 7,881,135
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Ethan H. Cannon
- G01 - MEASURING TESTING
Information Patent Grant
Carbon nanotube based integrated semiconductor circuit
- Patent number 7,786,466
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Joerg Appenzeller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for radiation tolerance by automated placement
- Patent number 7,774,732
- Issue date Aug 10, 2010
- International Business Machines Corporation
- AJ KleinOsowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-resetting, self-correcting latches
- Patent number 7,734,970
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Alan J. Drake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for radiation tolerance by implant well notching
- Patent number 7,725,870
- Issue date May 25, 2010
- International Business Machines Corporation
- Mark R. Beckenbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for radiation tolerance by logic book folding
- Patent number 7,698,681
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Mark R. Beckenbaugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for soft-error immune and self-correcting latches
- Patent number 7,590,907
- Issue date Sep 15, 2009
- International Business Machines Corporation
- Alan J. Drake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-resetting, self-correcting latches
- Patent number 7,418,641
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Alan J. Drake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic logic circuit apparatus and method for reducing leakage pow...
- Patent number 7,202,705
- Issue date Apr 10, 2007
- International Business Machines Corporation
- Hung Cai Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic logic circuit incorporating reduced leakage state-retaining...
- Patent number 7,193,446
- Issue date Mar 20, 2007
- International Business Machines Corporation
- Hung Cai Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT
- Publication number 20110263101
- Publication date Oct 27, 2011
- International Business Machines Corporation
- Joerg Appenzeller
- B82 - NANO-TECHNOLOGY
Information Patent Application
APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
- Publication number 20110102042
- Publication date May 5, 2011
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT
- Publication number 20100295025
- Publication date Nov 25, 2010
- International Business Machines Corporation
- Joerg Appenzeller
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacito...
- Publication number 20100271057
- Publication date Oct 28, 2010
- Ethan H. Cannon
- G01 - MEASURING TESTING
Information Patent Application
Radiation Tolerance by Clock Signal Interleaving
- Publication number 20090241073
- Publication date Sep 24, 2009
- Matthew R. Ellavsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT
- Publication number 20090179193
- Publication date Jul 16, 2009
- Joerg Appenzeller
- B82 - NANO-TECHNOLOGY
Information Patent Application
APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
- Publication number 20090134925
- Publication date May 28, 2009
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for Radiation Tolerance by Implant Well Notching
- Publication number 20090045841
- Publication date Feb 19, 2009
- Mark R. Beckenbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Radiation Tolerance by Automated Placement
- Publication number 20090049418
- Publication date Feb 19, 2009
- AJ KleinOsowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Radiation Tolerance by Logic Book Folding
- Publication number 20090045840
- Publication date Feb 19, 2009
- Mark R. Beckenbaugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR SOFT-ERROR IMMUNE AND SELF-CORRECTING LATCHES
- Publication number 20080270862
- Publication date Oct 30, 2008
- Alan J. Drake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Soft Error Modeling with Double Current Pulse
- Publication number 20080016477
- Publication date Jan 17, 2008
- AJ Kleinosowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-resetting, self-correcting latches
- Publication number 20070028157
- Publication date Feb 1, 2007
- Alan J. Drake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic logic circuit incorporating reduced leakage state-retaining...
- Publication number 20060103431
- Publication date May 18, 2006
- International Business Machines Corporation
- Hung Cai Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic logic circuit apparatus and method for reducing leakage pow...
- Publication number 20060082389
- Publication date Apr 20, 2006
- International Business Machines Corporation
- Hung Cai Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY

Aj KleinOsowski

Person

Patents Grantslast 30 patents

Apparatus and method for hardening latches in SOI CMOS devices

Radiation tolerance by clock signal interleaving

Carbon nanotube based integrated semiconductor circuit

Carbon nanotube based integrated semiconductor circuit

Apparatus and method for hardening latches in SOI CMOS devices

Method for QCRIT measurement in bulk CMOS using a switched capacito...

Carbon nanotube based integrated semiconductor circuit

Method for radiation tolerance by automated placement

Self-resetting, self-correcting latches

Method for radiation tolerance by implant well notching

Method for radiation tolerance by logic book folding

Method and apparatus for soft-error immune and self-correcting latches

Self-resetting, self-correcting latches

Dynamic logic circuit apparatus and method for reducing leakage pow...

Dynamic logic circuit incorporating reduced leakage state-retaining...

Patents Applicationslast 30 patents

CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT

APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT

Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacito...

Radiation Tolerance by Clock Signal Interleaving

CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT

APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

Method for Radiation Tolerance by Implant Well Notching

Method for Radiation Tolerance by Automated Placement

Method for Radiation Tolerance by Logic Book Folding

METHOD AND APPARATUS FOR SOFT-ERROR IMMUNE AND SELF-CORRECTING LATCHES

Method for Soft Error Modeling with Double Current Pulse

Self-resetting, self-correcting latches

Dynamic logic circuit incorporating reduced leakage state-retaining...

Dynamic logic circuit apparatus and method for reducing leakage pow...