Ajay Bhatia

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performing multiple bit computation and convolution in memory
- Patent number 11,914,973
- Issue date Feb 27, 2024
- Apple Inc.
- Shahzad Nazar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid pulse/two-stage data latch
- Patent number 11,870,442
- Issue date Jan 9, 2024
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power down detection for non-destructive isolation signal generation
- Patent number 11,579,642
- Issue date Feb 14, 2023
- Apple Inc.
- Vivekanandan Venugopal
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flip-flop circuit with glitch protection
- Patent number 11,496,120
- Issue date Nov 8, 2022
- Apple Inc.
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage clock swing tolerant sequential circuits for dynamic po...
- Patent number 11,424,734
- Issue date Aug 23, 2022
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid pulse/two-stage data latch
- Patent number 11,418,173
- Issue date Aug 16, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semi dynamic flop and single stage pulse flop with shadow latch and...
- Patent number 11,303,268
- Issue date Apr 12, 2022
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level-shifting transparent window sense amplifier
- Patent number 11,164,611
- Issue date Nov 2, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power flip-flop with balanced clock-to-Q delay
- Patent number 11,139,803
- Issue date Oct 5, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power down detection for non-destructive isolation signal generation
- Patent number 11,132,010
- Issue date Sep 28, 2021
- Apple Inc.
- Vivekanandan Venugopal
- G01 - MEASURING TESTING
Information Patent Grant
Low voltage clock swing tolerant sequential circuits for dynamic po...
- Patent number 11,018,653
- Issue date May 25, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulsed level shifter circuitry
- Patent number 10,903,824
- Issue date Jan 26, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level shifter with isolation on both input and output domains with...
- Patent number 10,838,483
- Issue date Nov 17, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid pulse/master-slave data latch
- Patent number 10,742,201
- Issue date Aug 11, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level-shifting transparent window sense amplifier
- Patent number 10,734,040
- Issue date Aug 4, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid power switch
- Patent number 10,732,693
- Issue date Aug 4, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed level shifter circuitry
- Patent number 10,581,412
- Issue date Mar 3, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low leakage power switch
- Patent number 10,523,194
- Issue date Dec 31, 2019
- Apple Inc.
- Jaroslav Raszka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flop circuit with integrated clock gating circuit
- Patent number 10,491,197
- Issue date Nov 26, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock gating circuit
- Patent number 10,461,747
- Issue date Oct 29, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid power switch
- Patent number 10,261,563
- Issue date Apr 16, 2019
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power detection circuit
- Patent number 10,191,086
- Issue date Jan 29, 2019
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Grant
Level shifting circuit with data resolution and grounded input nodes
- Patent number 10,187,061
- Issue date Jan 22, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced power set-reset latch based flip-flop
- Patent number 10,033,356
- Issue date Jul 24, 2018
- Apple Inc.
- Zhao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive diode sizing techniques for reducing memory power leakage
- Patent number 9,922,699
- Issue date Mar 20, 2018
- Apple Inc.
- Yildiz Sinangil
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic margin tuning for controlling custom circuits and memories
- Patent number 9,602,092
- Issue date Mar 21, 2017
- Apple Inc.
- Ajay Kumar Bhatia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power grid segmentation for memory arrays
- Patent number 9,529,533
- Issue date Dec 27, 2016
- Apple Inc.
- Michael A. Dreesen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage low leakage address decoder using multiple power modes
- Patent number 9,411,391
- Issue date Aug 9, 2016
- Apple Inc.
- Ajay Bhatia
- G11 - INFORMATION STORAGE
Information Patent Grant
Global write driver for memory array structure
- Patent number 9,411,392
- Issue date Aug 9, 2016
- Apple Inc.
- Ajay Bhatia
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM regulating retention scheme with discrete switch control and i...
- Patent number 9,411,406
- Issue date Aug 9, 2016
- Apple Inc.
- Bo Tang
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Performing Multiple Bit Computation and Convolution in Memory
- Publication number 20240231758
- Publication date Jul 11, 2024
- Apple Inc.
- Shahzad Nazar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Backside Routing Implementation in SRAM Arrays
- Publication number 20230298996
- Publication date Sep 21, 2023
- Apple Inc.
- Mohamed H. Abu-Rahma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Pulse/Two-Stage Data Latch
- Publication number 20220345117
- Publication date Oct 27, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip-Flop Circuit with Glitch Protection
- Publication number 20220231673
- Publication date Jul 21, 2022
- Apple Inc.
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Performing Multiple Bit Computation and Convolution in Memory
- Publication number 20220156045
- Publication date May 19, 2022
- Apple Inc.
- Shahzad Nazar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Bit Cell for In-Memory Computation
- Publication number 20220101914
- Publication date Mar 31, 2022
- Apple Inc.
- Michael A. Dreesen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Down Detection for Non-Destructive Isolation Signal Generation
- Publication number 20220043469
- Publication date Feb 10, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G01 - MEASURING TESTING
Information Patent Application
Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Po...
- Publication number 20210344329
- Publication date Nov 4, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semi Dynamic Flop and Single Stage Pulse Flop with Shadow Latch and...
- Publication number 20210167759
- Publication date Jun 3, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hybrid Pulse/Two-Stage Data Latch
- Publication number 20200373915
- Publication date Nov 26, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSED LEVEL SHIFTER CIRCUITRY
- Publication number 20200313660
- Publication date Oct 1, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND...
- Publication number 20200106424
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID PULSE/MASTER-SLAVE DATA LATCH
- Publication number 20200106425
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...
- Publication number 20200103957
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID POWER SWITCH
- Publication number 20190235602
- Publication date Aug 1, 2019
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LEAKAGE POWER SWITCH
- Publication number 20190097622
- Publication date Mar 28, 2019
- Apple Inc.
- Jaroslav Raszka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flop Circuit with Integrated Clock Gating Circuit
- Publication number 20190089337
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Power Clock Gating Circuit
- Publication number 20190089354
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP
- Publication number 20170366170
- Publication date Dec 21, 2017
- Apple Inc.
- Zhao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER DETECTION CIRCUIT
- Publication number 20170276705
- Publication date Sep 28, 2017
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES
- Publication number 20160191031
- Publication date Jun 30, 2016
- Apple Inc.
- Ajay Kumar Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE
- Publication number 20160055889
- Publication date Feb 25, 2016
- Apple Inc.
- Ajay Kumar Bhatia
- G11 - INFORMATION STORAGE
Information Patent Application
VOLTAGE SAMPLING SCHEME WITH DYNAMICALLY ADJUSTABLE SAMPLE RATES
- Publication number 20160043705
- Publication date Feb 11, 2016
- Apple Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES
- Publication number 20160043707
- Publication date Feb 11, 2016
- Apple Inc.
- Ajay Kumar Bhatia
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE
- Publication number 20150348600
- Publication date Dec 3, 2015
- Apple Inc.
- Ajay Kumar Bhatia
- G11 - INFORMATION STORAGE
Information Patent Application
GLOBAL WRITE DRIVER FOR MEMORY ARRAY STRUCTURE
- Publication number 20150227456
- Publication date Aug 13, 2015
- Apple Inc.
- Ajay Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LEAKAGE ADDRESS DECODER
- Publication number 20150227186
- Publication date Aug 13, 2015
- Apple Inc.
- Ajay Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE REGULATION FOR DATA RETENTION IN A VOLATILE MEMORY
- Publication number 20150228312
- Publication date Aug 13, 2015
- Apple Inc.
- Ajay Bhatia
- G11 - INFORMATION STORAGE
Information Patent Application
Wide Common Mode Range Sense Amplifier
- Publication number 20150207462
- Publication date Jul 23, 2015
- Apple Inc.
- Ajay Kumar Bhatia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Instantaneous IR Drop Measurement Circuit
- Publication number 20150102833
- Publication date Apr 16, 2015
- Apple Inc.
- Ajay K. Bhatia
- G01 - MEASURING TESTING

Ajay Bhatia

Person

Patents Grantslast 30 patents

Performing multiple bit computation and convolution in memory

Hybrid pulse/two-stage data latch

Power down detection for non-destructive isolation signal generation

Flip-flop circuit with glitch protection

Low voltage clock swing tolerant sequential circuits for dynamic po...

Hybrid pulse/two-stage data latch

Semi dynamic flop and single stage pulse flop with shadow latch and...

Level-shifting transparent window sense amplifier

Low power flip-flop with balanced clock-to-Q delay

Power down detection for non-destructive isolation signal generation

Low voltage clock swing tolerant sequential circuits for dynamic po...

Pulsed level shifter circuitry

Level shifter with isolation on both input and output domains with...

Hybrid pulse/master-slave data latch

Level-shifting transparent window sense amplifier

Hybrid power switch

Pulsed level shifter circuitry

Low leakage power switch

Flop circuit with integrated clock gating circuit

Low power clock gating circuit

Hybrid power switch

Power detection circuit

Level shifting circuit with data resolution and grounded input nodes

Reduced power set-reset latch based flip-flop

Adaptive diode sizing techniques for reducing memory power leakage

Dynamic margin tuning for controlling custom circuits and memories

Power grid segmentation for memory arrays

Multistage low leakage address decoder using multiple power modes

Global write driver for memory array structure

SRAM regulating retention scheme with discrete switch control and i...

Patents Applicationslast 30 patents

Performing Multiple Bit Computation and Convolution in Memory

Backside Routing Implementation in SRAM Arrays

Hybrid Pulse/Two-Stage Data Latch

Flip-Flop Circuit with Glitch Protection

Performing Multiple Bit Computation and Convolution in Memory

Memory Bit Cell for In-Memory Computation

Power Down Detection for Non-Destructive Isolation Signal Generation

Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Po...

Semi Dynamic Flop and Single Stage Pulse Flop with Shadow Latch and...

Hybrid Pulse/Two-Stage Data Latch

PULSED LEVEL SHIFTER CIRCUITRY

SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND...

HYBRID PULSE/MASTER-SLAVE DATA LATCH

LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...

HYBRID POWER SWITCH

LOW LEAKAGE POWER SWITCH

Flop Circuit with Integrated Clock Gating Circuit

Low Power Clock Gating Circuit

REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP

POWER DETECTION CIRCUIT

DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES

LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE

VOLTAGE SAMPLING SCHEME WITH DYNAMICALLY ADJUSTABLE SAMPLE RATES

DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES

CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE

GLOBAL WRITE DRIVER FOR MEMORY ARRAY STRUCTURE

LOW LEAKAGE ADDRESS DECODER

VOLTAGE REGULATION FOR DATA RETENTION IN A VOLATILE MEMORY

Wide Common Mode Range Sense Amplifier

Instantaneous IR Drop Measurement Circuit