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Ajay J. Joshi
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Lexington, MA, US
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last 30 patents
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Patent Grant
Gate-level mapping of integrated circuits using multi-spectral imaging
Patent number
10,282,833
Issue date
May 7, 2019
Trustees of Boston University
Ronen Adato
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Hierarchical error correction
Patent number
8,914,712
Issue date
Dec 16, 2014
FREESCALE SEMICONDUCTOR, INC.
Ravindraraj Ramaraju
H03 - BASIC ELECTRONIC CIRCUITRY
Patents Applications
last 30 patents
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Patent Application
PHOTONIC COMMUNICATION PLATFORM AND RELATED METHODS FOR INCREASING...
Publication number
20230388024
Publication date
Nov 30, 2023
Lightmatter, Inc
Mykhailo Tymchenko
H04 - ELECTRIC COMMUNICATION TECHNIQUE
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Patent Application
PHOTONIC COMMUNICATION PLATFORM AND RELATED ARCHITECTURES, SYSTEMS...
Publication number
20230314742
Publication date
Oct 5, 2023
Lightmattter, Inc.
Carlos Dorta-Quinones
G02 - OPTICS
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Patent Application
GATE-LEVEL MAPPING OF INTEGRATED CIRCUITS USING MULTI-SPECTRAL IMAGING
Publication number
20180350062
Publication date
Dec 6, 2018
Trustees of Boston University
Ronen Adato
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
HIERARCHICAL ERROR CORRECTION
Publication number
20130227368
Publication date
Aug 29, 2013
BOSTON UNIVERSITY
Ravindraraj Ramaraju
G06 - COMPUTING CALCULATING COUNTING