Ajay K. Ravi

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits with dual-edge clocking
- Patent number 8,912,834
- Issue date Dec 16, 2014
- Altera Corporation
- Ajay K. Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with dual-edge clocking
- Patent number 8,519,763
- Issue date Aug 27, 2013
- Altera Corporation
- Ajay K. Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Common clock path pessimism analysis for circuit designs using cloc...
- Patent number 8,205,178
- Issue date Jun 19, 2012
- Altera Corporation
- Ajay K Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of most critical timing paths in digital circuits
- Patent number 8,028,260
- Issue date Sep 27, 2011
- Altera Corporation
- Ajay K Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common clock path pessimism analysis for circuit designs using cloc...
- Patent number 7,926,019
- Issue date Apr 12, 2011
- Altera Corporation
- Ajay K Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to find worst-case setup and hold relationship for static t...
- Patent number 7,424,692
- Issue date Sep 9, 2008
- Altera Corporation
- Ajay K Ravi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING
- Publication number 20130328606
- Publication date Dec 12, 2013
- Altera Corporation
- Ajay K. Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING
- Publication number 20110304371
- Publication date Dec 15, 2011
- Ajay K. Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common Clock Path Pessimism Analysis for Circuit Designs Using Cloc...
- Publication number 20110239173
- Publication date Sep 29, 2011
- Ajay K. Ravi
- G06 - COMPUTING CALCULATING COUNTING