Ajay Nagarandal

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Sunnyvale, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Deterministic data latency in serializer/deserializer-based design...
- Patent number 11,860,751
- Issue date Jan 2, 2024
- Synopsys, Inc.
- Abhijeet Samudra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed functional protocol based test and debug
- Patent number 11,662,383
- Issue date May 30, 2023
- Synopsys, Inc.
- Anubhav Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraint based bit-stream compression in hardware for programmabl...
- Patent number 10,152,566
- Issue date Dec 11, 2018
- Altera Corporation
- Ajay Nagarandal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Behavioral simulation model for clock-data recovery phase-locked loop
- Patent number 9,898,561
- Issue date Feb 20, 2018
- Altera Corporation
- Bo Zhou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Automatic test pattern generation tool with feedback path capabilit...
- Patent number 7,539,957
- Issue date May 26, 2009
- Altera Corporation
- Ajay Nagarandal
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for automatically generating tests for programmable circ...
- Patent number 7,024,327
- Issue date Apr 4, 2006
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH-SPEED FUNCTIONAL PROTOCOL BASED TEST AND DEBUG
- Publication number 20220120811
- Publication date Apr 21, 2022
- Synopsys, Inc.
- Anubhav SINHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BEHAVIORAL SIMULATION MODEL FOR CLOCK-DATA RECOVERY PHASE-LOCKED LOOP
- Publication number 20160350455
- Publication date Dec 1, 2016
- Altera Corporation
- Bo Zhou
- G06 - COMPUTING CALCULATING COUNTING