Ajay Naini

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Core redundancy in a chip multiprocessor for highly reliable systems
- Patent number 7,328,371
- Issue date Feb 5, 2008
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection in dynamic logic circuits
- Patent number 6,954,912
- Issue date Oct 11, 2005
- Fujitsu Limited
- Pranjal Srivastava
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for reduction of noise sensitivity in dynamic...
- Patent number 6,603,333
- Issue date Aug 5, 2003
- Fujitsu Limited
- James Vinh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read port design and method for register array
- Patent number 6,542,423
- Issue date Apr 1, 2003
- Fujitsu Limited
- Vydhyanathan Kalyanasundharam
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Error detection in dynamic logic circuits
- Publication number 20030217307
- Publication date Nov 20, 2003
- Pranjal Srivastava
- G01 - MEASURING TESTING
Information Patent Application
Elimination of rounding step in the short path of a floating point...
- Publication number 20030115236
- Publication date Jun 19, 2003
- Ajay Naini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ PORT DESIGN AND METHOD FOR REGISTER ARRAY
- Publication number 20030058718
- Publication date Mar 27, 2003
- Vydhyanathan Kalyanasundharam
- G11 - INFORMATION STORAGE