Ajit K. Agarwal

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Hyderabad, IN

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Patents Grantslast 30 patents

Information Patent Grant
Splitting vector processing loops with an unknown trip count
- Patent number 12,182,552
- Issue date Dec 31, 2024
- Xilinx, Inc.
- Ajit K. Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded shared memory functional simulation of dataflow graph
- Patent number 11,036,546
- Issue date Jun 15, 2021
- Xilinx, Inc.
- Kumud Bhandari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compilation flow for a heterogeneous multi-core architecture
- Patent number 10,860,766
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Mukund Sivaraman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Dataflow Based Analysis Guidance to Mapper for Buffers Allocation i...
- Publication number 20240176942
- Publication date May 30, 2024
- Xilinx, Inc.
- Ajit K. Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCK AND BUFFER SCHEDULING IN MULTI-CORE ARCHITECTURES
- Publication number 20240028422
- Publication date Jan 25, 2024
- Xilinx, Inc.
- Ajit Kumar AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLITTING VECTOR PROCESSING LOOPS WITH AN UNKNOWN TRIP COUNT
- Publication number 20230385040
- Publication date Nov 30, 2023
- Xilinx, Inc.
- Ajit K. Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILATION FLOW FOR A HETEROGENEOUS MULTI-CORE ARCHITECTURE
- Publication number 20200372200
- Publication date Nov 26, 2020
- Xilinx, Inc.
- Mukund Sivaraman
- G06 - COMPUTING CALCULATING COUNTING