Akhil Garg

Person

Uttar Pradesh, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scan wrapper architecture for system-on-chip
- Patent number 11,320,485
- Issue date May 3, 2022
- NXP USA, INC.
- Akhil Garg
- G01 - MEASURING TESTING
Information Patent Grant
Test circuitry with annularly arranged compressor and decompressor...
- Patent number 10,747,922
- Issue date Aug 18, 2020
- Cadence Design Systems, Inc.
- Akhil Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Securing access to integrated circuit scan mode and data
- Patent number 10,222,417
- Issue date Mar 5, 2019
- Cadence Design Systems, Inc.
- Akhil Garg
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Testing of multi-clock domains
- Patent number 8,527,824
- Issue date Sep 3, 2013
- STMicroelectronics International N.V.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Grant
Locally synchronous shared BIST architecture for testing embedded m...
- Patent number 8,386,864
- Issue date Feb 26, 2013
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of multi-clock domains
- Patent number 8,381,051
- Issue date Feb 19, 2013
- STMicroelectronics International N.V.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Grant
System and method for efficient detection and restoration of data s...
- Patent number 8,352,781
- Issue date Jan 8, 2013
- STMicroelectronics International N.V.
- Akhil Garg
- G11 - INFORMATION STORAGE
Information Patent Grant
Locally synchronous shared BIST architecture for testing embedded m...
- Patent number 8,108,744
- Issue date Jan 31, 2012
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple embedded memories and testing components for the same
- Patent number 7,954,017
- Issue date May 31, 2011
- STMicroelectronics Pvt. Ltd.
- Amit Kashyap
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SINGLE EVENT UPSET HARDENED FLIP-FLOP AND METHODS OF OPERATION
- Publication number 20240372539
- Publication date Nov 7, 2024
- NXP B.V.
- Rishabh Kaistha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Design For Test For Source Synchronous Interfaces
- Publication number 20240192271
- Publication date Jun 13, 2024
- NXP B.V.
- Akhil Garg
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF MULTI-CLOCK DOMAINS
- Publication number 20130159802
- Publication date Jun 20, 2013
- STMicroelectronics International N.V
- Swapnil BAHL
- G01 - MEASURING TESTING
Information Patent Application
LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED M...
- Publication number 20120198291
- Publication date Aug 2, 2012
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF MULTI-CLOCK DOMAINS
- Publication number 20110264971
- Publication date Oct 27, 2011
- STMICROELECTRONICS PVT. LTD.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA S...
- Publication number 20100017651
- Publication date Jan 21, 2010
- STMICROELECTRONICS PVT. LTD.
- Akhil Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Locally synchronous shared BIST architecture for testing embedded m...
- Publication number 20080126892
- Publication date May 29, 2008
- STMicroelectronics Pvt. Ltd.
- Prashant Dubey
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple embedded memories and testing components for the same
- Publication number 20070162793
- Publication date Jul 12, 2007
- STMicroelectronics Pvt, Ltd.
- Amit Kashyap
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Scan wrapper architecture for system-on-chip

Test circuitry with annularly arranged compressor and decompressor...

Securing access to integrated circuit scan mode and data

Testing of multi-clock domains

Locally synchronous shared BIST architecture for testing embedded m...

Testing of multi-clock domains

System and method for efficient detection and restoration of data s...

Locally synchronous shared BIST architecture for testing embedded m...

Multiple embedded memories and testing components for the same

Patents Applicationslast 30 patents

SINGLE EVENT UPSET HARDENED FLIP-FLOP AND METHODS OF OPERATION

Design For Test For Source Synchronous Interfaces

TESTING OF MULTI-CLOCK DOMAINS

LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED M...

TESTING OF MULTI-CLOCK DOMAINS

SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA S...

Locally synchronous shared BIST architecture for testing embedded m...

Multiple embedded memories and testing components for the same