Akira Goda

Person

Setagaya, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Parallelized defect detection across multiple sub-blocks in a memor...
- Patent number 12,217,799
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive read disturb scan
- Patent number 12,216,915
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Animesh R. Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-gate string drivers having shared pillar structure
- Patent number 12,219,772
- Issue date Feb 4, 2025
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D NAND memory device devices and related electronic systems
- Patent number 12,199,070
- Issue date Jan 14, 2025
- Lodestar Licensing Group LLC
- Kunal R. Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Concurrent programming of retired wordline cells with dummy data
- Patent number 12,170,113
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including source gates
- Patent number 12,148,474
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick charge loss mitigation using two-pass controlled delay
- Patent number 12,131,060
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses including multiple channel materials within a tier stack
- Patent number 12,132,116
- Issue date Oct 29, 2024
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Read counter adjustment for delaying read disturb scans
- Patent number 12,131,788
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including in-tier driver circuit
- Patent number 12,100,454
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Jun Fujiki
- G11 - INFORMATION STORAGE
Information Patent Grant
Code rate as function of logical saturation
- Patent number 12,099,725
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of errors in data retrieved from a memory device to apply...
- Patent number 12,086,028
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic devices including control logic regions
- Patent number 12,080,700
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer allocation for reducing block transit penalty
- Patent number 12,079,517
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die cross-temperature management for a memory device
- Patent number 12,067,290
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic devices having a memory array region, a control log...
- Patent number 12,068,272
- Issue date Aug 20, 2024
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-pass corrective programming for memory cells that store multipl...
- Patent number 12,068,034
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices having source lines directly coupled to body regions...
- Patent number 12,062,396
- Issue date Aug 13, 2024
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory block programming using defectivity information
- Patent number 12,051,479
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Padding cached data with valid data for memory flush commands
- Patent number 12,019,557
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-pass programming of memory cells using temporary parity ge...
- Patent number 12,001,721
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer code rate architecture for special event protection wit...
- Patent number 11,994,947
- Issue date May 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device programming technique for increased bits per cell
- Patent number 11,960,722
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic devices including two-dimensional materials, and re...
- Patent number 11,943,919
- Issue date Mar 26, 2024
- Kamal M. Karda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices with backside bond pads under a memory array
- Patent number 11,935,853
- Issue date Mar 19, 2024
- Eric N. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Read-time overhead and power optimizations with command queues in m...
- Patent number 11,922,993
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Koichi Kawai
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified read counter incrementing scheme in a memory sub-system
- Patent number 11,922,029
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices including indium-containing materials, and related e...
- Patent number 11,908,948
- Issue date Feb 20, 2024
- Micron Technology, Inc.
- Kamal M. Karda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementing fault tolerant page stripes on low density memory systems
- Patent number 11,899,966
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICES INCLUDING MULTI-MATERIAL CHANNEL STRUCTURES
- Publication number 20250022962
- Publication date Jan 16, 2025
- Lodestar Licensing Group LLC
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY
- Publication number 20250013382
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20250014655
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS
- Publication number 20250006275
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
Reduction of Errors in Data Retrieved from a Memory Device to Apply...
- Publication number 20240419544
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT
- Publication number 20240420766
- Publication date Dec 19, 2024
- MICRON TECHNOLOGY, INC.
- Jun Fujiki
- G11 - INFORMATION STORAGE
Information Patent Application
CODE RATE AS FUNCTION OF LOGICAL SATURATION
- Publication number 20240411459
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS
- Publication number 20240413145
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES HAVING SIGNAL ROUTING STRUCTURES AT BONDING INTERFACES
- Publication number 20240404976
- Publication date Dec 5, 2024
- Lodestar Licensing Group LLC
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240393980
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS...
- Publication number 20240386966
- Publication date Nov 21, 2024
- Lodestar Licensing Group, LLC
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20240370206
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION
- Publication number 20240371452
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Pitamber Shukla
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Structures Comprising Vertical Channel Material and Havi...
- Publication number 20240357819
- Publication date Oct 24, 2024
- Lodestar Licensing Group LLC
- Guangyu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240347128
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO...
- Publication number 20240347126
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE
- Publication number 20240339163
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Leo Raimondo
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS
- Publication number 20240320144
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH BACKSIDE BOND PADS UNDER A MEMORY ARRAY
- Publication number 20240312933
- Publication date Sep 19, 2024
- Lodestar Licensing Group LLC
- Eric N. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS
- Publication number 20240311309
- Publication date Sep 19, 2024
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING ERASE BLOCKS COUPLED TO A SAME STRING AS ZONES
- Publication number 20240311036
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Daniel J. Hubbard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20240311057
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Daniel J. Hubbard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240302999
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-OPTIMIZING CORRECTIVE READ OFFSETS WITH LATERAL CHARGE MIGRATI...
- Publication number 20240231642
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Gianluca Nicosia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL
- Publication number 20240231617
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRING DRIVER ASSEMBLIES INCLUDING TWO-DIMENSIONAL MATERIALS, AND R...
- Publication number 20240224516
- Publication date Jul 4, 2024
- Lodestar Licensing Group LLC
- Kamal M. Karda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRITING USER DATA INTO STORAGE MEMORY
- Publication number 20240185926
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Application
READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20240168880
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20240168878
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20240168879
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Parallelized defect detection across multiple sub-blocks in a memor...

Adaptive read disturb scan

Multi-gate string drivers having shared pillar structure

3D NAND memory device devices and related electronic systems

Concurrent programming of retired wordline cells with dummy data

Apparatus and methods including source gates

Programming selective word lines during an erase operation in a mem...

Quick charge loss mitigation using two-pass controlled delay

Apparatuses including multiple channel materials within a tier stack

Read counter adjustment for delaying read disturb scans

Memory device including in-tier driver circuit

Code rate as function of logical saturation

Reduction of errors in data retrieved from a memory device to apply...

Microelectronic devices including control logic regions

Buffer allocation for reducing block transit penalty

On-die cross-temperature management for a memory device

Microelectronic devices having a memory array region, a control log...

Two-pass corrective programming for memory cells that store multipl...

Memory devices having source lines directly coupled to body regions...

Memory block programming using defectivity information

Padding cached data with valid data for memory flush commands

Multiple-pass programming of memory cells using temporary parity ge...

Multi-layer code rate architecture for special event protection wit...

Memory device programming technique for increased bits per cell

Microelectronic devices including two-dimensional materials, and re...

Memory devices with backside bond pads under a memory array

Read-time overhead and power optimizations with command queues in m...

Modified read counter incrementing scheme in a memory sub-system

Memory devices including indium-containing materials, and related e...

Implementing fault tolerant page stripes on low density memory systems

Patents Applicationslast 30 patents

MEMORY DEVICES INCLUDING MULTI-MATERIAL CHANNEL STRUCTURES

QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS

Reduction of Errors in Data Retrieved from a Memory Device to Apply...

MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT

CODE RATE AS FUNCTION OF LOGICAL SATURATION

MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS

MEMORY DEVICES HAVING SIGNAL ROUTING STRUCTURES AT BONDING INTERFACES

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS...

ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE

TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION

Integrated Structures Comprising Vertical Channel Material and Havi...

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO...

BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE

APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS

MEMORY DEVICES WITH BACKSIDE BOND PADS UNDER A MEMORY ARRAY

PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS

CONFIGURING ERASE BLOCKS COUPLED TO A SAME STRING AS ZONES

PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

SELF-OPTIMIZING CORRECTIVE READ OFFSETS WITH LATERAL CHARGE MIGRATI...

MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL

STRING DRIVER ASSEMBLIES INCLUDING TWO-DIMENSIONAL MATERIALS, AND R...

WRITING USER DATA INTO STORAGE MEMORY

READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...