Akira Goda

Person

Setagaya, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Memory devices with backside bond pads under a memory array
- Patent number 12,354,982
- Issue date Jul 8, 2025
- Eric N. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Write-once memory encoded data
- Patent number 12,334,154
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Xiangyu Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Sacrificial strings in a memory device to detect read disturb
- Patent number 12,334,142
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive pre-read management in multi-pass programming
- Patent number 12,334,153
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Using duplicate data for improving error correction capability
- Patent number 12,327,048
- Issue date Jun 10, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory programming using consecutive coarse-fine programming operat...
- Patent number 12,322,450
- Issue date Jun 3, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device programming technique for increased bits per cell
- Patent number 12,307,090
- Issue date May 20, 2025
- Micron Technology, Inc.
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory for programming data states of memory cells
- Patent number 12,293,790
- Issue date May 6, 2025
- Micron Technology, Inc.
- Koichi Kawai
- G11 - INFORMATION STORAGE
Information Patent Grant
String driver assemblies including two-dimensional materials, and r...
- Patent number 12,284,805
- Issue date Apr 22, 2025
- Lodestar Licensing Group LLC
- Kamal M. Karda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conditional valley tracking during corrective reads
- Patent number 12,266,407
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with non-linear delay variations for scheduling memory re...
- Patent number 12,249,364
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallelized defect detection across multiple sub-blocks in a memor...
- Patent number 12,217,799
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-gate string drivers having shared pillar structure
- Patent number 12,219,772
- Issue date Feb 4, 2025
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive read disturb scan
- Patent number 12,216,915
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Animesh R. Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D NAND memory device devices and related electronic systems
- Patent number 12,199,070
- Issue date Jan 14, 2025
- Lodestar Licensing Group LLC
- Kunal R. Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Concurrent programming of retired wordline cells with dummy data
- Patent number 12,170,113
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including source gates
- Patent number 12,148,474
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick charge loss mitigation using two-pass controlled delay
- Patent number 12,131,060
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses including multiple channel materials within a tier stack
- Patent number 12,132,116
- Issue date Oct 29, 2024
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Read counter adjustment for delaying read disturb scans
- Patent number 12,131,788
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including in-tier driver circuit
- Patent number 12,100,454
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Jun Fujiki
- G11 - INFORMATION STORAGE
Information Patent Grant
Code rate as function of logical saturation
- Patent number 12,099,725
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of errors in data retrieved from a memory device to apply...
- Patent number 12,086,028
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic devices including control logic regions
- Patent number 12,080,700
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer allocation for reducing block transit penalty
- Patent number 12,079,517
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die cross-temperature management for a memory device
- Patent number 12,067,290
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic devices having a memory array region, a control log...
- Patent number 12,068,272
- Issue date Aug 20, 2024
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-pass corrective programming for memory cells that store multipl...
- Patent number 12,068,034
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices having source lines directly coupled to body regions...
- Patent number 12,062,396
- Issue date Aug 13, 2024
- Akira Goda
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250226034
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
DRIVERS INCLUDING TWO-DIMENSIONAL MATERIALS, AND RELATED NON-VOLATI...
- Publication number 20250212402
- Publication date Jun 26, 2025
- Lodestar Licensing Group LLC
- Kamal M. Karda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READS
- Publication number 20250201316
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A PROGRAM BUFFER IN A...
- Publication number 20250190123
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY TO REDUCE STORAGE CAPACIT...
- Publication number 20250190122
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A HOST DATA BUFFER IN...
- Publication number 20250190140
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250181501
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Ashutosh Malshe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS WITH NON-LINEAR REFRESH MECHANISM AND METHODS FOR OPERATI...
- Publication number 20250182810
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY DEVICES
- Publication number 20250149511
- Publication date May 8, 2025
- Lodestar Licensing Group LLC
- Kunal R. Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...
- Publication number 20250140317
- Publication date May 1, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Application
LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE...
- Publication number 20250140323
- Publication date May 1, 2025
- Micron Technology, Inc.
- Xiangang Luo
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20250140322
- Publication date May 1, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
CALIBRATING DATA RELOCATION FROM BUFFER TO MEMORY DEVICE IN A MEMOR...
- Publication number 20250130736
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-GATE STRING DRIVERS HAVING SHARED PILLAR STRUCTURE
- Publication number 20250133740
- Publication date Apr 24, 2025
- Lodestar Licensing Group, LLC
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20250124982
- Publication date Apr 17, 2025
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20250087275
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
- Publication number 20250077416
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250077415
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA
- Publication number 20250078932
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20250053301
- Publication date Feb 13, 2025
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES INCLUDING MULTI-MATERIAL CHANNEL STRUCTURES
- Publication number 20250022962
- Publication date Jan 16, 2025
- Lodestar Licensing Group LLC
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY
- Publication number 20250013382
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20250014655
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS
- Publication number 20250006275
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
Reduction of Errors in Data Retrieved from a Memory Device to Apply...
- Publication number 20240419544
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT
- Publication number 20240420766
- Publication date Dec 19, 2024
- MICRON TECHNOLOGY, INC.
- Jun Fujiki
- G11 - INFORMATION STORAGE
Information Patent Application
CODE RATE AS FUNCTION OF LOGICAL SATURATION
- Publication number 20240411459
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS
- Publication number 20240413145
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES HAVING SIGNAL ROUTING STRUCTURES AT BONDING INTERFACES
- Publication number 20240404976
- Publication date Dec 5, 2024
- Lodestar Licensing Group LLC
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240393980
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Memory devices with backside bond pads under a memory array

Write-once memory encoded data

Sacrificial strings in a memory device to detect read disturb

Adaptive pre-read management in multi-pass programming

Using duplicate data for improving error correction capability

Memory programming using consecutive coarse-fine programming operat...

Memory device programming technique for increased bits per cell

Memory for programming data states of memory cells

String driver assemblies including two-dimensional materials, and r...

Conditional valley tracking during corrective reads

Apparatus with non-linear delay variations for scheduling memory re...

Parallelized defect detection across multiple sub-blocks in a memor...

Multi-gate string drivers having shared pillar structure

Adaptive read disturb scan

3D NAND memory device devices and related electronic systems

Concurrent programming of retired wordline cells with dummy data

Apparatus and methods including source gates

Programming selective word lines during an erase operation in a mem...

Quick charge loss mitigation using two-pass controlled delay

Apparatuses including multiple channel materials within a tier stack

Read counter adjustment for delaying read disturb scans

Memory device including in-tier driver circuit

Code rate as function of logical saturation

Reduction of errors in data retrieved from a memory device to apply...

Microelectronic devices including control logic regions

Buffer allocation for reducing block transit penalty

On-die cross-temperature management for a memory device

Microelectronic devices having a memory array region, a control log...

Two-pass corrective programming for memory cells that store multipl...

Memory devices having source lines directly coupled to body regions...

Patents Applicationslast 30 patents

PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

DRIVERS INCLUDING TWO-DIMENSIONAL MATERIALS, AND RELATED NON-VOLATI...

CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READS

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A PROGRAM BUFFER IN A...

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY TO REDUCE STORAGE CAPACIT...

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A HOST DATA BUFFER IN...

MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

APPARATUS WITH NON-LINEAR REFRESH MECHANISM AND METHODS FOR OPERATI...

NON-VOLATILE MEMORY DEVICES

PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...

LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE...

SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

CALIBRATING DATA RELOCATION FROM BUFFER TO MEMORY DEVICE IN A MEMOR...

MULTI-GATE STRING DRIVERS HAVING SHARED PILLAR STRUCTURE

APPARATUS AND METHODS INCLUDING SOURCE GATES

SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE

MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

MEMORY DEVICES INCLUDING MULTI-MATERIAL CHANNEL STRUCTURES

QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS

Reduction of Errors in Data Retrieved from a Memory Device to Apply...

MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT

CODE RATE AS FUNCTION OF LOGICAL SATURATION

MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS

MEMORY DEVICES HAVING SIGNAL ROUTING STRUCTURES AT BONDING INTERFACES

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY