Akshay Chada

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Folsom, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,615,584
- Issue date Mar 28, 2023
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,080,925
- Issue date Aug 3, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotaton
- Patent number 10,424,107
- Issue date Sep 24, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics with early stencil test
- Patent number 10,319,138
- Issue date Jun 11, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATION
- Publication number 20220051473
- Publication date Feb 17, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATON
- Publication number 20200098167
- Publication date Mar 26, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS WITH EARLY STENCIL TEST
- Publication number 20180286102
- Publication date Oct 4, 2018
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING